 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| ds07-13715-3e fujitsu semiconductor data sheet 16-bit proprietary microcontrollers cmos f 2 mc-16lx mb90560/565 series MB90561/561a/562/562a/f562/f562b/v560 mb90567/568/f568 n description the mb90560/565 series is a general-purpose 16-bit microcontroller designed for industrial, oa, and process control applications that require high-speed real-time processing. the device features a multi-function timer able to output a programmable waveform. the microcontroller instruction set is based on the same at architecture as the f 2 mc-8l and f 2 mc-16l families with additional instructions for high-level languages, extended addressing modes, enhanced signed multiplication and division instructions, and a complete range of bit manipulation instructions. the microcontroller has a 32-bit accumulator for processing long word (32-bit) data. n features ?clock ? internal oscillator circuit and pll clock multiplication circuit ? oscillation clock clock speed selectable from either the machine clock, main clock, or pll clock. the main clock is the oscillation clock divided into 2 (0.5 mhz to 8 mhz for a 1 mhz to 16 mhz base oscillation) . the pll clock is the oscillation clock multiplied by one to four (4 mhz to 16 mhz for a 4 mhz base oscillation) . ? minimum instruction execution time : 62.5 ns (for oscillation = 4 mhz, pll clock setting = 4, v cc = 5.0 v) ? maximum cpu memory space : 16 mb ? 24-bit addressing ? bank addressing (continued) n packages 64-pin plastic qfp 64-pin plastic lqfp 64-pin plastic sh-dip (fpt-64p-m06) (fpt-64p-m09) (dip-64p-m01)
mb90560/565 series 2 (continued) ? instruction set ? bit, byte, word, and long word data types ? 23 different addressing modes ? enhanced calculation precision using a 32-bit accumulator ? enhanced signed multiplication and division instructions and reti instruction ? instruction set designed for high level language (c) and multi-tasking ? uses a system stack pointer ? symmetric instruction set and barrel shift instructions ? program patch function (2 address pointers) . ? 4-byte instruction queue ? interrupt function ? priority levels are programmable ? 32 interrupts ? data transfer function ? extended intelligent i/o service function : up to 16 channels ? low-power consumption modes ? sleep mode (cpu operating clock stops.) ? timebase timer mode (only oscillation clock and timebase timer continue to operate.) ? stop mode (oscillation clock stops.) ? cpu intermittent operation mode (the cpu operates intermittently at the specified interval.) ? package ? lqfp-64p (ftp-64p-m09 : 0.65 mm pin pitch) ? qfp-64p (ftp-64p-m06 : 1.00 mm pin pitch) ? sh-dip (dip-64p-m01 : 1.778 mm pin pitch) ? process : cmos technology n peripheral functions (resources) ? i/o ports : 51 ports (max.) ? timebase timer : 1 channel ? watchdog timer : 1 channel ? 16-bit reload timer : 2 channel 5 ? multi-function timer ? 16-bit free-run timer : 1 channel ? output compare : 6 channels can output an interrupt request when a match occurs between the count in the 16-bit freerun timer and the value set in the compare register. ? input capture : 4 channels on detecting an active edge on the input signal from an external input pin, copies the count value of the 16- bit freerun timer to the input capture data register and generates an interrupt request. ? 8/16-bit ppg timer (8-bit 6 channels or 16-bit 3 channels) the period and duty of the output pulse can be set by the program. ? waveform generator (8-bit timer : 3 channels) ? uart : 2 channels ? full-duplex, double-buffered (8-bit) ? can be set to asynchronous or clock synchronous serial transfer (i/o expansion serial) operation ? dtp/external interrupt circuit (8 channels) ? external interrupts can activate the extended intelligent i/o service. ? generates interrupts in response to external interrupt inputs. mb90560/565 series 3 ? delayed interrupt generation module ? generates an interrupt request for task switching. ? 8/10-bit a/d converter : 8 channels ? 8-bit or 10-bit resolution selectable mb90560/565 series 4 n product lineup 1. mb90560 series * : dip switch setting (s2) when using the emulation pod (mb2145-507) . refer to 2.7 dedicated emulator power supply in the mb2145-507 hardware manual for details. part number mb90f562/b mb90562/a MB90561/a mb90v560 classification internal flash memory product internal mask rom product evaluation product rom size 64 kbytes 32 kbytes no rom ram size 2 kbytes 1 kbytes 4 kbytes dedicated emula- tor power supply * ?? no cpu functions number of instructions : 351 minimum instruction execution time : 62.5 ns for a 4 mhz oscillation (with 4 multiplier) addressing modes : 23 modes program patch function : 2 address pointers maximum memory space : 16 mbytes ports i/o ports (cmos) : 51 uart full-duplex, double-buffered clock synchronous or asynchronous operation selectable can be used as i/o serial internal dedicated baud rate generator 2 channels 16-bit reload timer 16-bit reload timer operation 2 channels multi-function timer 16-bit free-run timer 1 channel output compare 6 channels input capture 4 channels 8/16-bit ppg timer (8-bit 6 channels or 16-bit 3 channels) waveform generator (8-bit timer 3 channels) 3-phase waveform output, deadtime output 8/10-bit a/d converter 8 channels (multiplexed input) 8-bit or 10-bit resolution selectable conversion time : 6.13 m s (min.) (for maximum machine clock speed 16 mhz) dtp/external interrupts 8 channels (8 channels available, shared with a/d input) interrupt triggers : l ? h edge, h ? l edge, l level, h level (selectable) low power consumption modes sleep mode, timebase timer mode, stop mode, and cpu intermittent operation mode process cmos operating voltage 5 v 10 % mb90560/565 series 5 2. mb90565 series * : dip switch setting (s2) when using the emulation pod (mb2145-507) . refer to 2.7 dedicated emulator power supply in the mb2145-507 hardware manual for details. part number mb90f568 mb90568 mb90567 classification internal flash memory product internal mask rom product rom size 128 kbytes 96 kbytes ram size 4 kbytes 4 kbytes dedicated emula- tor power supply * ?? cpu functions number of instructions : 351 minimum instruction execution time : 62.5 ns for a 4 mhz oscillation (with 4 multiplier) addressing modes : 23 modes program patch function : 2 address pointers maximum memory space : 16 mbytes ports i/o ports (cmos) : 51 uart full-duplex, double-buffered clock synchronous or asynchronous operation selectable can be used as i/o serial internal dedicated baud rate generator 2 channels 16-bit reload timer 16-bit reload timer operation 2 channels multi-function timer 16-bit free-run timer 1 channel output compare 6 channels input capture 4 channels 8/16-bit ppg timer (8-bit 6 channels or 16-bit 3 channels) waveform generator (8-bit timer 3 channels) 3-phase waveform output, deadtime output 8/10-bit a/d converter 8 channels (multiplexed input) 8-bit or 10-bit resolution selectable conversion time : 6.13 m s (min.) (for maximum machine clock speed 16 mhz) dtp/external interrupts 8 channels (8 channels available, shared with a/d input) interrupt triggers : l ? h edge, h ? l edge, l level, h level (selectable) low power con- sumption modes sleep mode, timebase timer mode, stop mode, and cpu intermittent operation mode process cmos operating voltage 3.3 v 0.3 v mb90560/565 series 6 n package and corresponding products : available : not available note : see the package dimensions section for details of each package. package MB90561/a mb90562/a mb90f562/b mb90567 mb90568 mb90f568 mb90v560 fpt-64p-m09 (lqfp-0.65 mm) fpt-64p-m06 (qfp-1.00 mm) dip-64p-m01 (sh-dip) pga-256c-a01 (pga) mb90560/565 series 7 n pin assignments (continued) (top view) (fpt-64p-m06) * : n.c. on the mb90f568, mb90567, and mb90568. p44/ppg3 p45/ppg4 p46/ppg5 p50/an0 p51/an1 p52/an2 p53/an3 p54/an4 p55/an5 p56/an6 p57/an7 av cc avr av ss p60/sin1 p61/sot1 p62/sck1 p63/int7/dtti md0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 p30/rto0 v ss p27/in3 p26/in2 p25/in1 p24/in0 p23/to1 p22/tin1 p21/to0 p20/tin0 p17/frck p16/int6 p15/int5 p14/int4 p13/int3 p12/int2 p11/int1 p10/int0 p07 64 63 62 61 60 59 58 57 56 55 54 53 52 p43/ppg2 p42/ppg1 p41/ppg0 p40/sck0 p37/sot0 p36/sin0 c * v cc p35/rto5 p34/rto4 p33/rto3 p32/rto2 p31/rto1 20 21 22 23 24 25 26 27 28 29 30 31 32 rst md1 md2 x0 x1 v ss p00 p01 p02 p03 p04 p05 p06 mb90560/565 series 8 (continued) (top view) (fpt-64p-m09) * : n.c. on the mb90f568, mb90567, and mb90568. p45/ppg4 p46/ppg5 p50/an0 p51/an1 p52/an2 p53/an3 p54/an4 p55/an5 p56/an6 p57/an7 av cc avr av ss p60/sin1 p61/sot1 p62/sck1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 p27/in3 p26/in2 p25/in1 p24/in0 p23/to1 p22/tin1 p21/to0 p20/tin0 p17/frck p16/int6 p15/int5 p14/int4 p13/int3 p12/int2 p11/int1 p10/int0 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 p44/ppg3 p43/ppg2 p42/ppg1 p41/ppg0 p40/sck0 p37/sot0 p36/sin0 c * v cc p35/rto5 p34/rto4 p33/rto3 p32/rto2 p31/rto1 p30/rto0 v ss 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 p63/int7/dtti md0 rst md1 md2 x0 x1 v ss p00 p01 p02 p03 p04 p05 p06 p07 mb90560/565 series 9 (continued) (top view) (dip-64p-m01) (only support mb90f562/b, MB90561/a, and mb90562/a.) * : not support on the mb90f568, mb90567, and mb90568. c * p36/sin0 p37/sot0 p40/sck0 p41/ppg0 p42/ppg1 p43/ppg2 p44/ppg3 p45/ppg4 p46/ppg5 p50/an0 p51/an1 p52/an2 p53/an3 p54/an4 p55/an5 p56/an6 p57/an7 av cc avr av ss p60/sin1 p61/sot1 p62/sck1 p63/int7/dtti md0 rst md1 md2 x0 x1 v ss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 v cc p35/rto5 p34/rto4 p33/rto3 p32/rto2 p31/rto1 p30/rto0 v ss p27/in3 p26/in2 p25/in1 p24/in0 p23/to1 p22/tin1 p21/to0 p20/tin0 p17/frck p16/int6 p15/int5 p14/int4 p13/int3 p12/int2 p11/int1 p10/int0 p07 p06 p05 p04 p03 p02 p01 p00 mb90560/565 series 10 n pin descriotions * : see n i/o circuits for details of the circuit types. (continued) pin no. pin name circuit type * state/ function at reset description qfpm06 lqfpm09 sdip 23, 24 22, 23 30, 31 x0, x1 a oscillator connect oscillator to these pins. if using an external clock, leave x1 open. 20 19 27 rst b reset input external reset input pin 26 to 33 25 to 32 33 to 40 p00 to p07 c port inputs (hi-z outputs) i/o ports 34 to 40 33 to 39 41 to 47 p10 to p16 c i/o ports int0 to int6 can be used as interrupt request inputs ch0 to ch6. in standby mode, these pins can operate as inputs by setting the bits corresponding to en0 to en6 to 1 and setting as input ports. when used as a port, set the corresponding bits in the analog input enable register (ader) to port. 41 40 48 p17 c i/o port frck external clock input pin for the freerun timer. this pin can be used as an input when set as the clock input for the freerun timer and set as an input port. when used as a port, set the corresponding bit in the analog input enable register (ader) to port. 42 41 49 p20 d i/o port tin0 external clock input pin for reload timer ch0. this pin can be used as an input when set as the exter- nal clock input and set as an input port. 43 42 50 p21 d i/o port to0 event output pin for reload timer ch0. output oper- ates when event output is enabled. 44 43 51 p22 d i/o port tin1 external clock input pin for reload timer ch1. this pin can be used as an input when set as the exter- nal clock input and set as an input port. 45 44 52 p23 d i/o port to1 event output pin for reload timer ch1. output oper- ates when event output is enabled. 46 to 49 45 to 48 53 to 56 p24 to p27 d i/o ports in0 to in3 trigger input pins for input capture ch0 to ch3. these pins can be used as an input when set as an input capture trigger input and set as an input port. mb90560/565 series 11 * : see n i/o circuits for details of the circuit types. (continued) pin no. pin name cir- cuit type * state/ function at reset description qfpm06 lqfpm09 sdip 51 to 56 50 to 55 58 to 63 p30 to p35 e port inputs (hi-z) i/o ports rto0 to rto5 event output pins for the output compare and wave- form generator output pins. the pins output the specified waveform generated by the waveform generator. if not using waveform generation, these terminals enable output compare event output to use as output compare outputs. when used as a port, set the corresponding bits in the analog input enable register (ader) to port. 59 58 2 p36 d i/o port sin0 serial data input pin for uart ch0. this pin is used continuously when input operation is enabled for uart ch0. in this case, do not use as a general input pin. 60 59 3 p37 d i/o port sot0 serial data output pin for uart ch0. output operates when uart ch0 output is enabled. 61 60 4 p40 d i/o port sck0 serial clock i/o pin for uart ch0. output operates when uart ch0 clock output is enabled. 62 to 64, 1 to 3 61 to 64, 1, 2 5 to 10 p41 to p46 d i/o ports ppg0 to ppg5 output pins for ppg ch0 to ch5. the outputs operate when output is enabled for ppg ch0 to ch5. 4 to 11 3 to 10 11 to 18 p50 to p57 f analog inputs i/o ports an0 to an7 analog input pins for the a/d converter. input is available when the corresponding analog input en- able register bits are set. (ader : bit0 to bit7) 12 11 19 av cc ? power supply input v cc power supply input pin for a/d converter. 13 12 20 avr g refer- ence volt- age input reference voltage input pin for a/d converter. ensure that the voltage does not exceed v cc . 14 13 21 av ss ? power supply input v ss power supply input pin for a/d converter. mb90560/565 series 12 (continued) *1 : see n i/o circuits for details of the circuit types. *2 : n.c. on the mb90f568, mb90567, and mb90568 pin no. pin name circuit type *1 state/ function at reset description qfpm06 lqfpm09 sdip 15 14 22 p60 d port input (hi-z) i/o port sin1 serial data input pin for uart ch1. this pin is used continuously when input opera- tion is enabled for uart ch1. in this case, do not use as a general input pin. 16 15 23 p61 d i/o port sot1 serial data output pin for uart ch1. output operates when uart ch1 output is en- abled. 17 16 24 p62 d i/o port sck1 serial clock i/o pin for uart ch1. output operates when uart ch1 clock output is enabled. 18 17 25 p63 d i/o port int7 this pin can be used as interrupt request input ch7. in standby mode, this pin can operate as an input by setting the bit corresponding to en7 to 1 and setting as an input port. dtti fixed pin level input pin when rto0 to rto5 pins are used. input is enabled when input en- abled set in the waveform generator. 58 57 1 c *2 ? capacitor pin, pow- er supply input capacitor pin for stabilizing the power supply. connect an external ceramic capacitor of approx- imately 0.1 m f. 19 18 26 md0 b mode input pins input pin for setting the operation mode. connect directly to v cc or v ss . 21 20 28 md1 b input pin for setting the operation mode. connect directly to v cc or v ss . 22 21 29 md2 b input pin for setting the operation mode. connect directly to v ss . 25, 50 24, 49 32, 57 v ss ? power supply inputs power supply (gnd) input pin 57 56 64 v cc ? mb90560 series is power supply (5 v) input pin mb90565 series is power supply (3.3 v) input pin mb90560/565 series 13 n i/o circuits (continued) type circuit remarks a ? oscillation circuit internal oscillation feedback resistor (r f ) b ? cmos hysteresis reset input pin c ? cmos hysteresis i/o pin with pull-up control cmos output cmos hysteresis input (with input cut- off function in standby mode) internal pull-up resistor (r p ) < note > ? the pull-up resistor is active when the port is set as an input. d ? cmos hysteresis i/o pin cmos output cmos hysteresis input (with input cut- off function in standby mode) < notes > ? the i/o port output and internal resource output share the same out- put buffer. ? the i/o port input and internal resource input share the same input buffer. x1 xout x0 r f nch nch pch pch standby control signal reset input r p pout pull-up control nout input signal standby control signal pch nch pout nout input signal standby control signal pch nch mb90560/565 series 14 (continued) type circuit remarks e ?cmos i/o pin cmos output cmos hysteresis input (with input cut- off function in standby mode) < i ol = 12 ma > f ? analog/cmos hysteresis i/o pin cmos output cmos hysteresis input (with input cut- off function in standby mode) analog input (analog input to a/d con- verter is enabled when 1 is set in the corresponding bit in the analog input enable register (ader) .) ? the i/o port output and internal resource output share the same out- put buffer. ? the i/o port input and internal resource input share the same input buffer. g ? a/d converter (avr) voltage input pin pout nout hysteresis input standby control signal pch nch pout nout input signal standby control signal a/d converter analog input pch nch pch nch pch avr input analog input enable signal from a/d converter nch mb90560/565 series 15 n handling devices take note of the following nine points when handling devices : ? do not exceed maximum rated voltage (to prevent latch-up) ? supply voltage stability ? power-on precautions ? treatment of unused pins ? treatment of a/d converter power supply pins ? notes on using an external clock ? power supply pins ? sequence for connecting and disconnecting the a/d converter power supply and analog input pins ? notes on using the div a, ri and divw a, rwi instructions ? device handling precautions (1) do not exceed maximum rated voltage (to prevent latch-up) do not apply a voltage grater than v cc or less than v ss to the mb90560/565 series input or output pins. also ensure that the voltage between v cc and v ss does not exceed the rating. applying a voltage in excess of the ratings may result in latch-up causing thermal damage to circuit elements. similarly, when connecting or disconnecting the power to the analog power supply (av cc , avr) and analog inputs (an0 to an7) , ensure that the analog power supply voltages do not exceed the digital voltage (v cc ) . (2) supply voltage stability rapid changes in the v cc supply voltage may cause the device to misoperate. accordingly, ensure that the v cc power supply is stable. the standard for power supply voltage stability is a peak-to-peak v cc ripple voltage at the supply frequency (50 to 60 hz) of 10 % or less of v cc and a transient fluctuation in the voltage of 0.1 v/ms or less when turning the power supply on or off. (3) power-on precautions to prevent misoperation of the internal regulator circuit, ensure that the voltage rise time at power-on is at least 50 m s (between 0.2 v to 2.7 v) . (4) treatment of unused pins leaving unused input pins unconnected can cause misoperation or permanent damage to the device due to latchup. always pull-up or pull-down unused pins using a 2 k w or larger resistor. if some i/o pins are unused, either set as outputs and leave open circuit or set as inputs and treat in the same way as input pins. (5) treatment of a/d converter power supply pins if not using the a/d converter, connect the analog power supply pins so that av cc = avr = v cc and av ss = v ss . (6) notes on using an external clock even if using an external clock, an oscillation stabilization delay time occurs after a power-on reset and when recovering from stop mode in the same way as when an oscillator is connected. when using an external clock, drive the x0 pin only and leave the x1 pin open. mb90560/565 series 16 example of using an external clock (7) power supply pins the multiple v cc and v ss pins are connected together in the internal device design so as to prevent misoperation such as latch-up. however, always connect all v cc and v ss pins to the same potential externally to minimize spurious radiation, prevent misoperation of strobe signals due to increases in the ground level, and maintain the overall output current rating. also, ensure that the impedance of the v cc and v ss connections to the power supply is as low as possible. to minimize these problems, connect a bypass capacitor of approximately 0.1 m f between v cc and v ss . connect the capacitor close to the v cc and v ss pins. (8) sequence for connecting and disconnecting power supply do not apply voltage to the a/d converter power supply pins (av cc , avr, av ss ) or analog inputs (an0 to an7) until the digital power supply (v cc ) is turned on. when turning the device off, turn off the digital power supply after disconnecting the a/d converter power supply and analog inputs. when turning the power on or off, ensure that avr does not exceed av cc . when using the i/o ports that share pins with the analog inputs, ensure that the input voltage does not exceed av cc (turning the analog and digital power supplies on and off simultaneously is ok) . (9) conditions when output from ports 0 and 1 is undefined after turning on the power supply, the outputs from ports 0 and 1 are undefined during the oscillation stabilization delay time controlled by the regulator circuit (during the power-on reset) if the rst pin level is h. when the rst pin level is l, ports 0 and 1 go to high impedance. figures 1 and 2 show the timing (for the mb90f562/b and mb90v560) . note that this undefined output period does not occur on products without an internal regulator circuit as these products do not have an oscillation stabilization delay time. (MB90561/a, mb90562/a, mb90f568, and mb90567/8) x0 x1 open mb90560/565 series mb90560/565 series 17 ? figure 1 timing chart for undefined output from ports 0 and 1 (when rst pin level is h) oscillation stabilization delay time * 2 regulator circuit stabilization delay time * 1 v cc (power supply pin) ponr (power-on reset) signal rst (external asynchronous reset) signal rst (internal reset) signal oscillation clock signal ka (internal operating clock a) signal kb (internal operating clock b) signal port (port output) signal undefined output time *1 : regulator circuit oscillation stabilization delay time : 2 17 /oscillation clock frequency (approx. 8.19 ms for a 16 mhz oscillation clock frequency) *2 : oscillation stabilization delay time : 2 18 /oscillation clock frequency (approx. 16.38 ms for a 16 mhz oscillation clock frequency) mb90560/565 series 18 ? figure 2 timing chart for ports 0 and 1 going to high impedance state (when rst pin level is l) (10) notes on using the div a, ri and divw a, rwi instructions the location in which the remainder value produced by the signed division instructions div a, ri and divw a, rwi is stored depends on the bank register. the remainder is stored in an address in the memory bank specified in the bank register. set the bank register to 00 h when using the div a, ri and divw a, rwi instructions. (11) notes on using realos the extended intelligent i/o service (ei 2 os) cannot be used when using realos. (12) caution on operations during pll clock mode if the pll clock mode is selected in the microcontroller, it may attempt to continue the operation using the free- running frequency of the self oscillation circuit in the pll circuitry even if the oscillator is out of place or the clock input is stopped. performance of this operation, however, cannot be guaranteed. oscillation stabilization delay time * 2 regulator circuit stabilization delay time * 1 v cc (power supply pin) ponr (power-on reset) signal rst (external asynchronous reset) signal rst (internal reset) signal oscillation clock signal ka (internal operating clock a) signal kb (internal operating clock b) signal port (port output) signal high impedance *1 : regulator circuit oscillation stabilization delay time : 2 17 /oscillation clock frequency (approx. 8.19 ms for a 16 mhz oscillation clock frequency) *2 : oscillation stabilization delay time : 2 18 /oscillation clock frequency (approx. 16.38 ms for a 16 mhz oscillation clock frequency) mb90560/565 series 19 n block diagram f 2 mc-16lx cpu ram rom uart ch0 uart ch1 p00 p07 p10 p17 p20 p27 p30 p37 p40 p46 p50 p57 p60 p63 x0, x1 rst md0 to md2 sin0 sot0 sck0 sin1 sot1 sck1 int0 to int7 av cc avr av ss an0 to an7 to1 tin1 to0 tin0 ppg0 to ppg5 frck in0 to in3 rto0 rto1 rto2 rto3 rto4 rto5 dtti clock control circuit interrupt controller 8/16-bit ppg timer ch0 to ch5 * input capture ch0 to ch3 16-bit freerun timer output compare ch0 to ch5 waveform generator circuit 8/10-bit a/d converter 16-bit reload timer ch0 16-bit reload timer ch1 dtp/ external interrupts internal data bus i/o ports (ports 0, 1, 2, 3, 4, 5, and 6) * : channel numbers when used as 8-bit timers. three channels (ch1, ch3, and ch5) are available when used as 16-bit timers. note: the i/o ports share pins with the various peripheral functions (resources) . see the pin assignment and pin description sections for details. note that, if a pin is used by a peripheral function (resource) , it may not be used as an i/o port. mb90560/565 series 20 n memory map memory map of mb90560/565 series notes : when specified in the rom mirror function register, the upper part of 00 bank (004000 h to 00ffff h ) contains a mirror of the data in the upper part of ff bank (ff4000 h to ffffff h ) . see 10. rom mirror function selection module in the peripheral functions section for details of the rom mirror function settings. remarks : the rom mirror function is provided so the c compilers small memory model can be used. the lower 16 bits of the ff bank and 00 bank addresses are the same. however, as the ff bank rom area exceeds 48 kbytes, the entire rom data area cannot be mirrored in 00 bank. when using the c compilers small memory model, locating data tables in the area ff4000 h to ffffff h makes the image of the data visible in the 004000 h to 00ffff h area. this means that data tables located in rom can be referenced without needing to declare far pointers. ffffff h ff0000 h 010000 h 004000 h 000100 h 0000c0 h 000000 h single chip mode (with rom mirror function) rom area address #1 rom area (image of ff bank) address #2 address #3 ram area registers peripherals access prohibited * : v products do not contain internal rom. treat this address as the rom decode area used by the tools. part no. address#1 address#2 address#3 MB90561/a ff8000 h 008000 h 000500 h mb90562/a ff0000 h 004000 h 000900 h mb90f562/b ff0000 h 004000 h 000900 h mb90567 fe8000 h 004000 h 001100 h mb90568 fe0000 h 004000 h 001100 h mb90f568 fe0000 h 004000 h 001100 h mb90v560 fe0000 h * 004000 h * 001100 h mb90560/565 series 21 n i/o map (continued) address abbreviat- ed register name register name read/ write resource name initial value 000000 h pdr0 port 0 data register r/w port 0 xxxxxxxx b 000001 h pdr1 port 1 data register r/w port 1 xxxxxxxx b 000002 h pdr2 port 2 data register r/w port 2 xxxxxxxx b 000003 h pdr3 port 3 data register r/w port 3 xxxxxxxx b 000004 h pdr4 port 4 data register r/w port 4 xxxxxxxx b 000005 h pdr5 port 5 data register r/w port 5 xxxxxxxx b 000006 h pdr6 port 6 data register r/w port 6 xxxxxxxx b 000007 h to 00000f h access prohibited 000010 h ddr0 port 0 direction register r/w port 0 0 0 0 0 0 0 0 0 b 000011 h ddr1 port 1 direction register r/w port 1 0 0 0 0 0 0 0 0 b 000012 h ddr2 port 2 direction register r/w port 2 0 0 0 0 0 0 0 0 b 000013 h ddr3 port 3 direction register r/w port 3 0 0 0 0 0 0 0 0 b 000014 h ddr4 port 4 direction register r/w port 4 x 0 0 0 0 0 0 0 b 000015 h ddr5 port 5 direction register r/w port 5 0 0 0 0 0 0 0 0 b 000016 h ddr6 port 6 direction register r/w port 6 xxxx 0 0 0 0 b 000017 h ader analog input enable register r/w port 5, a/d converter 1 1 1 1 1 1 1 1 b 000018 h to 00001f h access prohibited 000020 h smr0 mode register ch0 r/w uart0 0 0 0 0 0 x 0 0 b 000021 h scr0 control register ch0 w, r/w 0 0 0 0 0 1 0 0 b 000022 h sidr0 input data register ch0 r xxxxxxxx b sodr0 output data register ch0 w 000023 h ssr0 status register ch0 r, r/w 0 0 0 0 1 0 0 0 b 000024 h smr1 mode register ch1 r/w uart1 0 0 0 0 0 x 0 0 b 000025 h scr1 control register ch1 w, r/w 0 0 0 0 0 1 0 0 b 000026 h sidr1 input data register ch1 r xxxxxxxx b sodr1 output data register ch1 w 000027 h ssr1 status register ch1 r, r/w 0 0 0 0 1 0 0 0 b 000028 h access prohibited 000029 h cdcr0 communication prescaler control register ch0 r/w communication prescaler 0 xxx 0 0 0 0 b mb90560/565 series 22 (continued) address abbreviat- ed register name register name read/ write resource name initial value 00002a h access prohibited 00002b h cdcr1 communication prescaler control register ch1 r/w communication prescaler 0 xxx 0 0 0 0 b 00002c h to 00002f h access prohibited 000030 h enir dtp/external interrupt enable register r/w dtp/external interrupts 0 0 0 0 0 0 0 0 b 000031 h eirr dtp/external interrupt request register r/w xxxxxxxx b 000032 h elvr request level setting register (lower) r/w 0 0 0 0 0 0 0 0 b 000033 h request level setting register (upper) r/w 0 0 0 0 0 0 0 0 b 000034 h adcs0 a/d control status register (lower) r/w 8/10-bit a/d converter 0 0 0 0 0 0 0 0 b 000035 h adcs1 a/d control status register (upper) w, r/w 0 0 0 0 0 0 0 0 b 000036 h adcr0 a/d data register (lower) r xxxxxxxx b 000037 h adcr1 a/d data register (upper) r, w 0 0 0 0 0 xxx b 000038 h prll0 ppg reload register ch0 (lower) r/w 8/16-bit ppg timer xxxxxxxx b 000039 h prlh0 ppg reload register ch0 (upper) r/w xxxxxxxx b 00003a h prll1 ppg reload register ch1 (lower) r/w xxxxxxxx b 00003b h prlh1 ppg reload register ch1 (upper) r/w xxxxxxxx b 00003c h ppgc0 ppg control register ch0 (lower) r/w 0 0 0 0 0 0 0 1 b 00003d h ppgc1 ppg control register ch1 (upper) r/w 0 0 0 0 0 0 0 1 b 00003e h pcs01 ppg clock control register ch0, ch1 r/w 0 0 0 0 0 0 xx b 00003f h access prohibited 000040 h prll2 ppg reload register ch2 (lower) r/w 8/16-bit ppg timer xxxxxxxx b 000041 h prlh2 ppg reload register ch2 (upper) r/w xxxxxxxx b 000042 h prll3 ppg reload register ch3 (lower) r/w xxxxxxxx b 000043 h prlh3 ppg reload register ch3 (upper) r/w xxxxxxxx b 000044 h ppgc2 ppg control register ch2 (lower) r/w 0 0 0 0 0 0 0 1 b 000045 h ppgc3 ppg control register ch3 (upper) r/w 0 0 0 0 0 0 0 1 b 000046 h pcs23 ppg clock control register ch2, ch3 r/w 0 0 0 0 0 0 xx b 000047 h access prohibited 000048 h prll4 ppg reload register ch4 (lower) r/w 8/16-bit ppg timer xxxxxxxx b 000049 h prlh4 ppg reload register ch4 (upper) r/w xxxxxxxx b 00004a h prll5 ppg reload register ch5 (lower) r/w xxxxxxxx b 00004b h prlh5 ppg reload register ch5 (upper) r/w xxxxxxxx b 00004c h ppgc4 ppg control register ch4 (lower) r/w 0 0 0 0 0 0 0 1 b mb90560/565 series 23 (continued) address abbreviat- ed register name register name read/ write resource name initial value 00004d h ppgc5 ppg control register ch5 (upper) r/w 8/16-bit ppg timer 0 0 0 0 0 0 0 1 b 00004e h pcs45 ppg clock control register ch4, ch5 r/w 0 0 0 0 0 0 xx b 00004f h access prohibited 000050 h tmrr0 8-bit reload register ch0 r/w waveform generator xxxxxxxx b 000051 h dtcr0 8-bit timer control register ch0 r/w 0 0 0 0 0 0 0 0 b 000052 h tmrr1 8-bit reload register ch1 r/w xxxxxxxx b 000053 h dtcr1 8-bit timer control register ch1 r/w 0 0 0 0 0 0 0 0 b 000054 h tmrr2 8-bit reload register ch2 r/w xxxxxxxx b 000055 h dtcr2 8-bit timer control register ch2 r/w 0 0 0 0 0 0 0 0 b 000056 h sigcr waveform control register r/w 0 0 0 0 0 0 0 0 b 000057 h access prohibited 000058 h cpclr compare clear register (lower) r/w 16-bit freerun timer xxxxxxxx b 000059 h compare clear register (upper) r/w xxxxxxxx b 00005a h tcdt timer data register (lower) r/w 0 0 0 0 0 0 0 0 b 00005b h timer data register (upper) r/w 0 0 0 0 0 0 0 0 b 00005c h tccs timer control/status register (lower) r/w 0 0 0 0 0 0 0 0 b 00005d h timer control/status register (upper) r/w 0 xx 0 0 0 0 0 b 00005e h access prohibited 00005f h 000060 h ipcp0 input capture data register ch0 (lower) r input capture xxxxxxxx b 000061 h input capture data register ch0 (upper) r xxxxxxxx b 000062 h ipcp1 input capture data register ch1 (lower) r xxxxxxxx b 000063 h input capture data register ch1 (upper) r xxxxxxxx b 000064 h ipcp2 input capture data register ch2 (lower) r xxxxxxxx b 000065 h input capture data register ch2 (upper) r xxxxxxxx b 000066 h ipcp3 input capture data register ch3 (lower) r xxxxxxxx b 000067 h input capture data register ch3 (upper) r xxxxxxxx b 000068 h ics01 input capture control register 01 r/w 0 0 0 0 0 0 0 0 b 000069 h access prohibited 00006a h ics23 input capture control register 23 r/w input capture 0 0 0 0 0 0 0 0 b 00006b h to 00006e h access prohibited mb90560/565 series 24 (continued) address abbreviat- ed register name register name read/ write resource name initial value 00006f h romm rom mirror function selection register w rom mirror function selection module xxxxxxx 1 b 000070 h occp0 compare register ch0 (lower) r/w output compare xxxxxxxx b 000071 h compare register ch0 (upper) r/w xxxxxxxx b 000072 h occp1 compare register ch1 (lower) r/w xxxxxxxx b 000073 h compare register ch1 (upper) r/w xxxxxxxx b 000074 h occp2 compare register ch2 (lower) r/w xxxxxxxx b 000075 h compare register ch2 (upper) r/w xxxxxxxx b 000076 h occp3 compare register ch3 (lower) r/w xxxxxxxx b 000077 h compare register ch3 (upper) r/w xxxxxxxx b 000078 h occp4 compare register ch4 (lower) r/w xxxxxxxx b 000079 h compare register ch4 (upper) r/w xxxxxxxx b 00007a h occp5 compare register ch5 (lower) r/w xxxxxxxx b 00007b h compare register ch5 (upper) r/w xxxxxxxx b 00007c h ocs0 compare control register ch0 (lower) r/w 0 0 0 0 xx 0 0 b 00007d h ocs1 compare control register ch1 (upper) r/w xxx 0 0 0 0 0 b 00007e h ocs2 compare control register ch2 (lower) r/w 0 0 0 0 xx 0 0 b 00007f h ocs3 compare control register ch3 (upper) r/w xxx 0 0 0 0 0 b 000080 h ocs4 compare control register ch4 (lower) r/w 0 0 0 0 xx 0 0 b 000081 h ocs5 compare control register ch5 (upper) r/w xxx 0 0 0 0 0 b 000082 h tmcsr0 : l timer control status register ch0 (lower) r/w 16-bit reload timer 0 0 0 0 0 0 0 0 b 000083 h tmcsr0 : h timer control status register ch0 (upper) r/w xxxx 0 0 0 0 b 000084 h tmr0 16-bit timer register ch0 (lower) r xxxxxxxx b tmrlr0 16-bit reload register ch0 (lower) w xxxxxxxx b 000085 h tmr0 16-bit timer register ch0 (upper) r xxxxxxxx b tmrhr0 16-bit reload register ch0 (upper) w xxxxxxxx b 000086 h tmcsr1 : l timer control status register ch1 (lower) r/w 0 0 0 0 0 0 0 0 b 000087 h tmcsr1 : h timer control status register ch1 (upper) r/w xxxx 0 0 0 0 b 000088 h tmr1 16-bit timer register ch1 (lower) r xxxxxxxx b tmrlr1 16-bit reload register ch1 (lower) w xxxxxxxx b 000089 h tmr1 16-bit timer register ch1 (upper) r xxxxxxxx b tmrhr1 16-bit reload register ch1 (upper) w xxxxxxxx b mb90560/565 series 25 (continued) address abbreviat- ed register name register name read/ write resource name initial value 00008a h to 00008b h access prohibited 00008c h rdr0 port 0 pull-up resistor setting register r/w port 0 0 0 0 0 0 0 0 0 b 00008d h rdr1 port 1 pull-up resistor setting register r/w port 1 0 0 0 0 0 0 0 0 b 00008e h to 00009d h access prohibited 00009e h pacsr program address detection control status register r/w address match detection 0 0 0 0 0 0 0 0 b 00009f h dirr delayed interrupt request/clear register r/w delayed interrupt xxxxxxx 0 b 0000a0 h lpmcr low power consumption mode register w, r/w low power consumption control circuit 0 0 0 1 1 0 0 0 b 0000a1 h ckscr clock selection register r, r/w clock 1 1 1 1 1 1 0 0 b 0000a2 h to 0000a7 h access prohibited 0000a8 h wdtc watchdog control register r/w watchdog timer 1 xxxx 1 1 1 b 0000a9 h tbtc timebase timer control register w, r/w timebase timer 1 xx 0 0 1 0 0 b 0000aa h to 0000ad h access prohibited 0000ae h fmcs flash memory control status register r, w, r/w flash memory 0 0 0 0 0 0 0 0 b 0000af h access prohibited 0000b0 h icr00 interrupt control register 00 (for writing) w, r/w interrupts xxxx 0 1 1 1 b interrupt control register 00 (for reading) r, r/w xx 0 0 0 1 1 1 b 0000b1 h icr01 interrupt control register 01 (for writing) w, r/w xxxx 0 1 1 1 b interrupt control register 01 (for reading) r, r/w xx 0 0 0 1 1 1 b 0000b2 h icr02 interrupt control register 02 (for writing) w, r/w xxxx 0 1 1 1 b interrupt control register 02 (for reading) r, r/w xx 0 0 0 1 1 1 b 0000b3 h icr03 interrupt control register 03 (for writing) w, r/w xxxx 0 1 1 1 b interrupt control register 03 (for reading) r, r/w xx 0 0 0 1 1 1 b 0000b4 h icr04 interrupt control register 04 (for writing) w, r/w xxxx 0 1 1 1 b interrupt control register 04 (for reading) r, r/w xx 0 0 0 1 1 1 b 0000b5 h icr05 interrupt control register 05 (for writing) w, r/w xxxx 0 1 1 1 b interrupt control register 05 (for reading) r, r/w xx 0 0 0 1 1 1 b mb90560/565 series 26 (continued) address abbreviat- ed register name register name read/ write resource name initial value 0000b6 h icr06 interrupt control register 06 (for writing) w, r/w interrupts xxxx 0 1 1 1 b interrupt control register 06 (for reading) r, r/w xx 0 0 0 1 1 1 b 0000b7 h icr07 interrupt control register 07 (for writing) w, r/w xxxx 0 1 1 1 b interrupt control register 07 (for reading) r, r/w xx 0 0 0 1 1 1 b 0000b8 h icr08 interrupt control register 08 (for writing) w, r/w xxxx 0 1 1 1 b interrupt control register 08 (for reading) r, r/w xx 0 0 0 1 1 1 b 0000b9 h icr09 interrupt control register 09 (for writing) w, r/w xxxx 0 1 1 1 b interrupt control register 09 (for reading) r, r/w xx 0 0 0 1 1 1 b 0000ba h icr10 interrupt control register 10 (for writing) w, r/w xxxx 0 1 1 1 b interrupt control register 10 (for reading) r, r/w xx 0 0 0 1 1 1 b 0000bb h icr11 interrupt control register 11 (for writing) w, r/w xxxx 0 1 1 1 b interrupt control register 11 (for reading) r, r/w xx 0 0 0 1 1 1 b 0000bc h icr12 interrupt control register 12 (for writing) w, r/w xxxx 0 1 1 1 b interrupt control register 12 (for reading) r, r/w xx 0 0 0 1 1 1 b 0000bd h icr13 interrupt control register 13 (for writing) w, r/w xxxx 0 1 1 1 b interrupt control register 13 (for reading) r, r/w xx 0 0 0 1 1 1 b 0000be h icr14 interrupt control register 14 (for writing) w, r/w xxxx 0 1 1 1 b interrupt control register 14 (for reading) r, r/w xx 0 0 0 1 1 1 b 0000bf h icr15 interrupt control register 15 (for writing) w, r/w xxxx 0 1 1 1 b interrupt control register 15 (for reading) r, r/w xx 0 0 0 1 1 1 b 0000c0 h to 0000ff h unused area 000100 h to # h ram area # h to 001fef h reserved area 001ff0 h padr0 program address detection register ch0 (lower) r/w address match detection xxxxxxxx b 001ff1 h program address detection register ch0 (middle) r/w xxxxxxxx b 001ff2 h program address detection register ch0 (lower) r/w xxxxxxxx b mb90560/565 series 27 (continued) ? read/write notation ? initial value notation address abbreviat- ed register name register name read/ write resource name initial value 001ff3 h padr1 program address detection register ch1 (lower) r/w address match detection xxxxxxxx b 001ff4 h program address detection register ch1 (middle) r/w xxxxxxxx b 001ff5 h program address detection register ch1 (lower) r/w xxxxxxxx b 001ff6 h to 001fff h unused area r/w : reading and writing permitted r : read-only w : write-only 0 : initial value is 0. 1 : initial value is 1. x : initial value is undefined. mb90560/565 series 28 n interrupts, interrut vectors, and interrupt control registers interrupt ei 2 os sup- port interrupt vector interrupt control register priori- ty no. * address icr address reset #08 08 h ffffdc h ?? high int 9 instruction #09 09 h ffffd8 h ?? exception #10 0a h ffffd4 h ?? a/d converter conversion complete #11 0b h ffffd0 h icr00 0000b0 h output compare channel 0 match #13 0d h ffffc8 h icr01 0000b1 h 8/16-bit ppg timer 0 counter borrow #14 0e h ffffc4 h output compare channel 1 match #15 0f h ffffc0 h icr02 0000b2 h 8/16-bit ppg timer 1 counter borrow #16 10 h ffffbc h output compare channel 2 match #17 11 h ffffb8 h icr03 0000b3 h 8/16-bit ppg timer 2 counter borrow #18 12 h ffffb4 h output compare channel 3 match #19 13 h ffffb0 h icr04 0000b4 h 8/16-bit ppg timer 3 counter borrow #20 14 h ffffac h output compare channel 4 match #21 15 h ffffa8 h icr05 0000b5 h 8/16-bit ppg timer 4 counter borrow #22 16 h ffffa4 h output compare channel 5 match #23 17 h ffffa0 h icr06 0000b6 h 8/16-bit ppg timer 5 counter borrow #24 18 h ffff9c h dtp/external interrupt channel 0/1 detection #25 19 h ffff98 h icr07 0000b7 h dtp/external interrupt channel 2/3 detection #26 1a h ffff94 h dtp/external interrupt channel 4/5 detection #27 1b h ffff90 h icr08 0000b8 h dtp/external interrupt channel 6/7 detection #28 1c h ffff8c h 8-bit timer 0/1/2 counter borrow #29 1d h ffff88 h icr09 0000b9 h 16-bit reload timer 0 underflow #30 1e h ffff84 h 16-bit freerun timer overflow #31 1f h ffff80 h icr10 0000ba h 16-bit reload timer 1 underflow #32 20 h ffff7c h input capture channel 0/1 #33 21 h ffff78 h icr11 0000bb h 16-bit freerun timer clear #34 22 h ffff74 h input capture channel 2/3 #35 23 h ffff70 h icr12 0000bc h timebase timer #36 24 h ffff6c h uart1 receive #37 25 h ffff68 h icr13 0000bd h uart1 send #38 26 h ffff64 h uart0 receive #39 27 h ffff60 h icr14 0000be h uart0 send #40 28 h ffff5c h flash memory status #41 29 h ffff58 h icr15 0000bf h delay interrupt output module #42 2a h ffff54 h low mb90560/565 series 29 : supported : not supported : supported, includes ei 2 os stop function : available if the interrupt that shares the same icr is not used. * : if two or more interrupts with the same level occur simultaneously, the interrupt with the lower interrupt vector number has priority mb90560/565 series 30 n peripheral functions 1. i/o ports ? the i/o ports can be used as general-purpose i/o ports (parallel i/o ports) . the mb90560/565 series have 7 ports (51 pins) . the ports share pins with the inputs and outputs of the peripheral functions. ? the port data registers (pdr) are used to output data to the i/o pins and read the data input from the i/o ports. similarly, the port direction registers (ddr) set the i/o direction (input or output) for each individual port bit. ? the following table lists the i/o ports and the peripheral functions with which they share pins. notes : pins p30 to p35 of port 3 can drive a maximum of i ol = 12 ma. port 5 shares pins with the analog inputs. when using port 5 pins as a general-purpose ports, ensure that the corresponding analog input enable register (ader) bits are set to 0 b . ader is initialized to ff h after a reset. ? block diagram for port 0 and 1 pins pin name (port) pin name (peripheral) peripheral function that shares pin port 0 p00-p07 ? not shared port 1 p10-p16 int0-int6 external interrupts p17 frck freerun timer external input port 2 p20-p23 tin0, to0, tin1, to1 16-bit reload timer 0 and 1 p24-p27 in0-in3 input capture 0 to 3 port 3 p30-p35 rto0-rto5 output compare p36, p37 sin0, sot0 uart0 port 4 p40 sck0 uart0 p41-p46 ppg0-ppg5 8/16-bit ppg timer port 5 p50-p57 an0-an7 8/10-bit a/d converter port 6 p60-p62 sin1, sot1, sck1 uart1 p63 int7 external interrupts dtti waveform generator internal data bus pull-up resistor setting register (pdrx) pdrx read pdrx write port data register (pdrx) port direction register (ddrx) input/output selection circuit input buffer output buffer standby control (lpmcr : spl = "1") port pin internal pull-up resistor mb90560/565 series 31 ? block diagram for port 2, 3, 4, and 6 pins ? block diagram for port 5 pins notes : when using as an input port, set the corresponding bit in the port 5 direction register (ddr5) to 0 and set the corresponding bit in the analog input enable register (ader) to 0. when using as an analog input pin, set the corresponding bit in the port 5 direction register (ddr5) to 0 and set the corresponding bit in the analog input enable register (ader) to 1. internal data bus pdrx read pdrx write port data register (pdrx) port direction register (ddrx) resource input input/output selection circuit resource output control signal resource output input buffer output buffer standby control (lpmcr : spl = "1") port pin internal data bus analog input enable register (ader) pdr5 read pdr5 write port data register (pdr5) port direction register (ddr5) input/output selection circuit analog converter analog input signal input buffer output buffer standby control (lpmcr : spl = "1") port 5 pin mb90560/565 series 32 2. timebase timer ? the timebase timer is an 18-bit freerun timer (timebase timer/counter) that counts up synchronized with the main clock (oscillation clock : hclk divided into 2) . ? the timer can generate interrupt requests at a specified interval, with four different interval time settings available. ? the timer supplies the operating clock for peripheral functions including the oscillation stabilization delay timer and watchdog timer. ? timebase timer interval settings notes : hclk : oscillation clock frequency the values enclosed in ( ) indicate the times for a clock frequency of 4 mhz. ? period of clocks supplied from timebase timer notes : hclk : oscillation clock frequency the values enclosed in ( ) indicate the times for a clock frequency of 4 mhz. internal count clock period interval time 2/hclk (0.5 m s) 2 12 /hclk (approx. 1.024 ms) 2 14 /hclk (approx. 4.096 ms) 2 16 /hclk (approx. 16.384 ms) 2 19 /hclk (approx. 131.072 ms) peripheral function clock period oscillation stabilization delay for the main clock 2 10 /hclk (approx. 0.256 ms) 2 13 /hclk (approx. 2.048 ms) 2 15 /hclk (approx. 8.192 ms) 2 17 /hclk (approx. 32.768 ms) watchdog timer 2 12 /hclk (approx. 1.024 ms) 2 14 /hclk (approx. 4.096 ms) 2 16 /hclk (approx. 16.384 ms) 2 19 /hclk (approx. 131.072 ms) mb90560/565 series 33 ? block diagram the actual interrupt request number for the timebase timer is : interrupt request number : #36 (24 h ) tbie tbof tbr tbc1 tbc0 2 1 2 2 2 3 2 8 2 9 2 10 2 11 2 12 2 13 2 14 2 15 2 16 2 17 2 18 of of of of to ppg timer to watchdog timer timebase timer/counter hclk divided into 2 to oscillation stabilization delay time selector in clock controller reset * 1 clear stop mode, etc. * 2 switch clock mode * 3 counter clear circuit tbof clear tbof set interval timer selector timebase timer control register (tbtc) timebase timer interrupt signal of : overflow hclk : oscillation clock frequency *1 : power-on reset, watchdog reset *2 : recovery from stop mode and timebase timer mode *3 : main ? pll clock mb90560/565 series 34 3. watchdog timer ? the watchdog timer is a timer/counter used to detect faults such as program runaway. ? the watchdog timer is a 2-bit counter that counts the clock signal from the timebase timer or clock timer. ? once started, the watchdog timer must be cleared before the 2-bit counter overflows. if an overflow occurs, the cpu is reset. ? interval time for the watchdog timer notes : the difference between the maximum and minimum watchdog timer interval times is due to the timing when the counter is cleared. as the watchdog timer is a 2-bit counter that counts the carry-up signal from the timebase timer or clock timer, clearing the timebase timer (when operating on hclk) or the clock timer (when operating on sclk) lengthens the time until the watchdog timer reset is generated. ? watchdog timer count clock ? events that stop the watchdog timer 1 : stop due to a power-on reset 2 : watchdog reset ? events that clear the watchdog timer 1 : external reset input from the rst pin. 2 : writing 0 to the software reset bit. 3 : writing 0 to the watchdog control bit (second and subsequent times) . 4 : changing to sleep mode (clears the watchdog timer and temporarily halts the count) . 5 : changing to timebase timer mode (clears the watchdog timer and temporarily halts the count) . 6 : changing to stop mode (clears the watchdog timer and temporarily halts the count) . hclk : oscillation clock (4 mhz) min. max. clock period approx. 3.58 ms approx. 4.61 ms 2 14 2 11 / hclk approx. 14.33 ms approx. 18.30 ms 2 16 2 13 / hclk approx. 57.23 ms approx. 73.73 ms 2 18 2 15 / hclk approx. 458.75 ms approx. 589.82 ms 2 18 2 15 / hclk wtc : wdcs hclk : oscillation clock pclk : pll clock 0 prohibited setting 1 count the timebase timer output. mb90560/565 series 35 ? block diagram ponr stbr wrst erst srst wte wt1 wt0 2 1 2 2 2 8 2 9 2 10 2 11 2 12 2 13 2 14 2 15 2 16 2 17 2 18 2 4 watchdog timer control register (wdtc) watchdog timer reset change to sleep mode change to stop mode change to timebase timer mode counter clear control circuit counter clock selector 2-bit counter start clear watchdog timer reset generation circuit to internal reset circuit main clock (hclk divided into 2) (timebase timer/counter) hclk : oscillation clock frequency mb90560/565 series 36 4. 16-bit reload timers 0 and 1 (with event count function) ? the 16-bit reload timers have the following functions. ? the count clock can be selected from three internal clocks or the external event clock. ? an interrupt to the cpu can be generated when an underflow occurs on 16-bit reload timer 0 or 1. this interrupt allows the timers to be used as interval timers. ? two different operation modes can be selected when an underflow occurs on 16-bit reload timer 0 or 1: one- shot mode in which timer operation halts when an underflow occurs or reload mode in which the value in the reload register is loaded into the timer and counting continues. ? extended intelligent i/o service (ei 2 os) is supported. ? the mb90560/565 series contains two 16-bit reload timer channels. ? 16-bit reload timer operation modes ? interval times for the 16-bit reload timers note : the values enclosed in ( ) and the example of interval times is for a machine clock frequency of 16 mhz. f is the machine clock frequency value for the calculation. remarks : 16-bit reload timer 0 can be used to generate the baud rate for uart0. 16-bit reload timer 1 can be used to generate the baud rate for uart1 and activation trigger for the a/d converter. count clock start trigger operation when an underflow occurs internal clock software trigger one-shot mode reload mode external trigger one-shot mode reload mode event count mode (external clock mode) software trigger one-shot mode reload mode count clock count clock period example of interval times internal clock 2 1 / f (0.125 m s) 0.125 m s to 8.192 ms 2 3 / f (0.5 m s) 0.5 m s to 32.768 ms 2 5 / f (2.0 m s) 2.0 m s to 131.1 ms event count mode 2 3 / f or longer 0.5 m s or longer mb90560/565 series 37 ? block diagram tmrlr0 *1 tmrlr1 *2 tmr0 *1 tmr1 *2 clk tin0 *1 tin1 *2 uf en to0 *1 to1 *2 clk 3 3 2 ???? csl1 csl0 mod2 mod1 mod0 oute outl reld uf inte cnte trg *4 internal data bus 16-bit reload register reload signal reload control circuit 16-bit timer register count clock generation circuit machine clock f prescaler gate input clock pulse detection circuit clear trigger internal clock pin input control circuit external clock clock selector select signal function selection timer control status register (tmcsr) wait signal to uart0 *1 to uart1 and a/d converter trigger *2 output control circuit output signal generation circuit pin operation control circuit interrupt request output # 30 (1e h ) * 1, * 3 # 32 (20 h ) * 2, * 3 *1 : channel 0 *2 : channel 1 *3 : interrupt number *4 : underflow mb90560/565 series 38 5. multi-function timer ? based on the 16-bit freerun timer, the multi-function timer can be used to generate 12 independent waveform outputs and to measure input pulse widths and external clock periods. ? structure of multi-function timer ? 16-bit freerun timer (1 channel) the 16-bit freerun timer consists of a 16-bit up-counter (timer data register (tcdt) ) , compare clear register (cpclr) , timer control status register (tccs) , and prescaler. the count output value from the 16-bit freerun timer provides the base time for the input capture and output compare functions. ? the count clock can be selected from the following eight clocks : 1/ f , 2/ f , 4/ f , 8/ f , 16/ f , 32/ f , 64/ f , 128/ f f : machine clock frequency ? an interrupt can be generated when the 16-bit freerun timer overflows or when the 16-bit freerun timer count is cleared to 0000 h due to a match occurring between the value in the compare clear register (cpclr) and the count in the 16-bit freerun timer (tccs : icre = 1, mode = 1) . ? the 16-bit freerun timer is cleared to 0000 h when a reset occurs, on setting the timer clear bit (sclr) in the timer control status register (tccs) , when a compare match occurs between the 16-bit freerun timer count and the value in the compare clear register (cpclr) (tccs : mode = 1) , or by writing 0000 h to the timer data register (tcdt) . ? output compare (6 channels) the output compare unit consists of compare registers (occp0 to occp5) , compare control registers (ocs0 to ocs5) , and compare output latches. when a match occurs between a compare register (occp0 to occp5) value and the count from the 16-bit freerun timer, the output compare can invert the level of the corresponding output compare pin and generate an interrupt. ? the compare registers (occp0 to occp5) operate independently for each channel. each of the compare registers (occp0 to occp5) has a corresponding output pin and an interrupt request flag in the channels compare control register (lower) (ocs0, ocs2, ocs4) . ? two channels of the compare registers (occp0 to occp5) can be used to invert the output pins. ? an interrupt can be output when a match occurs between a compare register (occp0 to occp5) and the count from the 16-bit freerun timer (ocs0, ocs2, ocs4 : iop0 = 1, iop1 = 1) . (ocs0, ocs2, ocs4 : ioe0 = 1, ioe1 = 1) ? the initial output levels for the output compare pins can be set. ? input capture (4 channels) the input capture consists of external input pins (in0 to in3) , corresponding input capture data registers (ipcp0 to ipcp3) , and input capture control status registers (ics01, ics23) . the input capture can transfer the count value from the 16-bit freerun timer to the input capture data register (ipcp0 to ipcp3) and output an interrupt on detecting an active edge on the signal input from the external input pin. ? each channel of the input capture operates independently. ? the active edge (rising edge, falling edge, or either edge) on the external signal can be specified. 16-bit freerun timer 16-bit output compare 16-bit input capture 8/16-bit ppg timer waveform generator 1 ch 6 ch 4 ch 8 bit 6 ch 16 bit 3 ch 8-bit timer 3 ch mb90560/565 series 39 ? an interrupt can be generated when an active edge is detected on the external signal (ics01, ics23 : ice0 = 1, ice1 = 1, ice2 = 1, ice3 = 1) . ? 8/16-bit ppg timer (8-bit : 6 channels, 16-bit : 3 channels) the 8/16-bit ppg timer consists of an 8-bit down counter (pcnt) , ppg control registers (ppgc0 to ppgc 5) , ppg clock control registers (pcs01, pcs23, pcs45) , and ppg reload registers (prll0 to prll5, prlh0 to prlh5) . when used as an 8/16-bit reload timer, the ppg operates as an event timer. the ppg can also be used to output pulses with specified frequency and duty ratio. ? 8-bit ppg mode each channel operates as an independent 8-bit ppg. ? 8-bit prescaler + 8-bit ppg mode ch0 (ch2, ch4) operates as an 8-bit prescaler and ch1 (ch3, ch5) operates as a variable frequency ppg by counting up on the borrow output from ch0 (ch2, ch4) . ? 16-bit ppg mode ch0 (ch2, ch4) and ch1 (ch3, ch5) operate together as a 16-bit ppg. ? ppg operation outputs pulses with the specified frequency and duty ratio (ratio of h level period and l level period), and can also be used as a d/a converter when combined with an external circuit. ? waveform generator the waveform generator consists of an 8-bit timer, 8-bit timer control registers (dtcr0 to dtcr2) , 8-bit reload registers (tmrr0 to tmrr2) , and waveform control register (sigcr) . the waveform generator can generate a dc chopper output or non-overlapping three-phase waveform output for inverter control using the realtime outputs (rt0 to rt5) and 8/16-bit ppg timer. ? a non-overlapping waveform can be generated by using the 8-bit timer as a deadtime timer and adding a non- overlap time delay to the ppg timer pulse output. (deadtime timer function) ? a non-overlapping waveform can be generated by using the 8-bit timer as a deadtime timer and adding a non- overlap time delay to the realtime outputs (rt1, rt3, rt5) . (deadtime timer function) ? a gate signal can be generated when a match occurs between the count from the 16-bit freerun timer and compare register in the output compare (occp0 to occp5) (rising edge on realtime output (rt) ) to control the ppg timer operation. (gate function) ? can control the rto0 to rto5 pin outputs using the dtti pin input. by making the dtti pin input clockless, the pins can be controlled externally even when the oscillation clock is halted. (the level for each pin can be set by the program.) however, the i/o ports (p30 to p35) must have been set beforehand as outputs and the output values set in the port 3 data register (pdr3) . mb90560/565 series 40 ? block diagram ? 16 - bit freerun timer , input capture , and output compare f ivf 8 ivfe stop mode sclr clk2 clk1 clk0 iclr iop1 iop0 ioe1 ioe0 icp0 icp1 ice0 ice1 eg11 eg10 eg01 eg00 in0/2 in1/3 cmod tq tq icre ms13 to 0 3 16 16 16 4 4 4 internal data bus to interrupt #31 (1f h ) * divider clock 16-bit freerun timer 16-bit compare clear register compare circuit compare registers 0, 2, 4 compare circuit compare registers 1, 3, 5 compare circuit to interrupt #34 (22 h ) * to a/d trigger to rt0, 2, 4 waveform generator to rt1, 3, 5 waveform generator to interrupts capture registers 0, 2 edge detection capture registers 1, 3 edge detection to interrupts # 13 (0d h ) * , # 17 (11 h ) * , # 21 (15 h ) * # 15 (0f h ) * , # 19 (13 h ) * , # 23 (17 h ) * # 33 (21 h ) * , # 35 (23 h ) * # 33 (21 h ) * , # 35 (23 h ) * * : interrupt number f : machine clock frequency mb90560/565 series 41 ? block diagram of 8/16-bit ppg timer f f pc02 pc01 pcnt0 pc00 pos0 oen0 sst0 poe0 puf0 pie0 pc12 pc11 pc10 pos1 oen1 sst1 poe1 puf1 pie1 gate0/1 gate1 prll0/2/4 prlh0/2/4 prlbh0/2/4 prll1/3/5 prlh1/3/5 prlbh1/3/5 internal data bus to interrupt #14 (0e h ) * selector divider operation control operation control (down counter) selector selector to ppg0, 2, 4 reload ch1, 3, 5 borrow l/h selector to interrupt #16 (10 h ) * ch0, 2, 4 borrow selector divider (down counter) selector selector to ppg1, 3, 5 reload l/h selector pcnt1 * : interrupt number f : machine clock frequency mb90560/565 series 42 ? block diagram of waveform generator f dck2 dck1 dck0 tmd1 tmd0 nrsl dtil dtie dtti to0 to1 rto0/u rto1/x rto2/v rto3/y rto4/w rto5/z u x to2 to3 v y to4 to5 w rt4 rt5 rt2 rt3 rt0 rt1 internal data bus divider clock dtti control circuit to gate0, 1 (to ppg timer) waveform generator 8-bit timer compare circuit selector selector 8-bit timer register 0 deadtime generation to gate2, 3 (to ppg timer) waveform generator waveform generator 8-bit timer compare circuit selector selector 8-bit timer register 1 deadtime generation to gate4, 5 (to ppg timer) 8-bit timer compare circuit selector selector 8-bit timer register 2 deadtime generation f : machine clock frequency mb90560/565 series 43 6. uart (1) overview ? the uart is a general-purpose serial communications interface for performing synchronous or asynchronous (start-stop synchronization) communications with external devices. ? the interface provides both a bi-directional communication function (normal mode) and a master-slave com- munication function (multi-processor mode) . ? the uart can generate interrupt requests at receive complete, receive error detected, and transmit complete timings. also the uart supports ei 2 os. ? uart functions the uart is a general-purpose serial communications interface for sending serial data to and from other cpus and peripheral devices. note : the uart does not add the start and stop bits in clock synchronous mode. in this case, only data is transmitted. function data buffer full-duplex double-buffered transmission modes ? clock synchronous (no start and stop bits) ? clock asynchronous (start-stop synchronization) baud rate ? max. 2 mhz (for a 16 mhz machine clock) ? baud rate generated by dedicated baud rate generator ? baud rate generated by external clock (clock input from sck0 and sck1 pins) ? baud rate generated by internal clock (clock supplied from 16-bit reload timer) ? eight different baud rate settings are available. number of data bits ? 7 bits (asynchronous normal mode only) ? 8 bits signal format non return to zero (nrz) format receive error detection ? framing errors ? overrun errors ? parity errors (not available in multi-processor mode) interrupt requests ? receive interrupt (receive complete or receive error detected) ? transmit interrupt (transmission complete) ? both transmit and receive support the extended intelligent i/o service (ei 2 os) . master/slave communication function (multi-processor mode) used for 1 (master) to n (slave) communications. (can only be used as master) mb90560/565 series 44 ? uart operation modes ? : not available *1 : the + 1 represents the address/data (a/d) bit used for communication control. *2 : only 1 stop bit supported for receiving. ? uart interrupts and ei 2 os : the uart has a function to halt ei 2 os if a receive error is detected. : available when the interrupt shared with icr13 or icr14 is not used. operation mode no. of data bits synchronization no. of stop bits no parity with parity 0 normal mode 7 or 8 bits asynchronous 1 or 2 bits *2 1 multi-processor mode 8 + 1 *1 ? asynchronous 2 clock synchronous mode 8 ? synchronous none interrupt interrupt no. interrupt control register vector table address ei 2 os register name address lower upper bank uart1 receive interrupt #37 (25 h ) icr13 0000bd h ffff68 h ffff69 h ffff6a h uart1 send interrupt #38 (26 h ) icr13 0000bd h ffff64 h ffff65 h ffff66 h uart0 receive interrupt #39 (27 h ) icr14 0000be h ffff60 h ffff61 h ffff62 h uart0 send interrupt #40 (28 h ) icr14 0000be h ffff5c h ffff5d h ffff5e h mb90560/565 series 45 (2) uart structure the uart consists of the following 11 blocks: ? block diagram ? clock selector ? mode registers (smr0, smr1) ? receive control circuit ? control registers (scr0, scr1) ? transmission control circuit ? status registers (ssr0, ssr1) ? receive status evaluation circuit ? input data registers (sidr0, sidr1) ? receive shift register ? output data registers (sodr0, sodr1) ? transmission shift register md1 md0 cs2 cs1 cs0 scke soe pen p sbl cl a/d rec rxe txe pe ore fre rdrf tdre bds rie tie sidr0/sidr1 p40/sck0 mb90560/565 series 46 ? clock selector selects the send/receive clock from either the dedicated baud rate generator, external input clock (clock input to sck0 or sck1 pin) , or internal clock (clock supplied by 16-bit reload timer) . ? receive control circuit the receive control circuit consists of a receive bit counter, start bit detection circuit, and receive parity counter. the receive bit counter counts the received data bits and outputs a receive interrupt request when the required number of data bits have been received. the start bit detection circuit detects the start bit on the serial input signal. on detecting a start bit, the receive data is shifted to the input data register (sidr0 or sidr1) in accordance with the specified transfer speed. the receive parity counter calculates the parity of the received data if parity is selected. ? transmission control circuit the transmission control circuit consists of a transmission bit counter, transmission start circuit, and transmission parity counter. the transmission bit counter counts the transmitted data bits and outputs a transmit interrupt request when the required number of data bits have been sent. the transmission start circuit starts transmission when data is written to the output data register (sodr0 or sodr1) . the transmission parity counter generates the parity bit for the transmitted data when parity is selected. ? receive shift register the receive shift register captures the data input from the sin0 or sin1 pin by shifting one bit at a time then transfers the received data to the input data register (sidr0 or sidr1) when reception completes. ? transmission shift register the transmission data is transferred from the output data register (sodr0 or sodr1) to the transmission shift register and output from the sot0 or sot1 pin by shifting one bit at a time. ? mode register (smr0, smr1) set the operation mode, baud rate clock and serial clock input/output control, and enables output for the serial data pin. ? control register (scr0, scr1) specifies whether to use parity, the type of parity, number of stop bits and data bits and the frame data format for operation mode 1, to clear the receive error flag bit, and to enable or disable send and receive operation. ? status register (ssr0, ssr1) stores the send/receive and error status information, set the serial data transfer direction, and enables or disables the send and receive interrupt requests. ? input data register (sidr0, sidr1) stores the received data. ? output data register (sodr0, sodr1) set the transmission data. the data set in the output data register is converted to serial format and output. mb90560/565 series 47 7. dtp/external interrupt circuit (1) overview of the dtp/external interrupt circuit the dtp (data transfer peripheral) /external interrupt circuit detects interrupt requests input to the external interrupt input pins (int7 to int0) and outputs interrupt requests. ? dtp/external interrupt circuit functions the dtp/external interrupt function detects edge or level signals input to the external interrupt input pins (int7 to int0) and outputs interrupt requests. the interrupt request is received by the cpu and, if the extended intelligent i/o service (ei 2 os) is enabled, ei 2 os performs automatic data transfer (dtp function) then passes control to the interrupt handler routine on completion. if ei 2 os is disabled, control passes directly to the interrupt handler routine without performing automatic data transfer (dtp function) . ? overview of the dtp/external interrupt circuit ? dtp/external interrupt circuit interrupts and ei 2 os : available when the interrupt shared with icr07 or icr08 is not used. channel interrupt no. interrupt control register vector table address ei 2 os register name address lower upper bank int0/int1 #25 (19 h ) icr07 0000b7 h ffff98 h ffff99 h ffff9a h int2/int3 #26 (1a h ) ffff94 h ffff95 h ffff96 h int4/int5 #27 (1b h ) icr08 0000b8 h ffff90 h ffff91 h ffff92 h int6/int7 #28 (1c h ) ffff8c h ffff8d h ffff8e h icr : interrupt control register external interrupt dtp function input pins 8 channels (p10/int0 to p16/int6, p63/int7) interrupt conditions the level or edge to detect can be set independently for each pin in the detection lev- el setup register (elvr) . l level, h level, rising edge, or falling edge input interrupt number #25 (19 h ) to #28 (1c h ) interrupt control interrupts can be enabled or disabled in the dtp/external interrupt enable register (enir) . interrupt flag the dtp/external interrupt request register (enrr) stores interrupt requests. processing selection set ei 2 os to disabled (icr : ise = 0) set ei 2 os to enabled (icr : ise = 1) operation jumps to interrupt handler routine jumps to interrupt handler routine after automatic data transfer by ei 2 os com- pletes. mb90560/565 series 48 (2) structure of the dtp/external interrupt circuit the dtp/external interrupt circuit consists of the following four blocks : ? dtp/interrupt detection circuit ? dtp/interrupt request register (eirr) ? dtp/interrupt enable register (enir) ? request level setting register (elvr) ? block diagram lb7 er7 er6 er5 er4 er3 er2 er1 er0 en7 en6 en5 en4 en3 en2 en1 en0 p63/int7 p10/int0 la7 lb6 la6 lb5 la5 lb4 la4 lb3 la3 lb2 la2 lb1 la1 lb0 la0 p16/int6 p11/int1 p12/int2 p13/int3 p15/int5 p14/int4 #25 (19 h )* #26 (1a h )* #27 (1b h )* #28 (1c h )* 22222222 internal data bus request level setting register (elvr) pin pin pin pin selector selector selector selector selector selector selector selector pin pin pin pin dtp/external interrupt input detection circuit dtp/interrupt request register (eirr) dtp/interrupt enable register (enir) interrupt request signal * : interrupt number mb90560/565 series 49 8. delayed interrupt generation module ? the delayed interrupt generation module is used to generate the task switching interrupt. generation of this hardware interrupt can be specified by software. ? delayed interrupt generation module functions ? block diagram function and control interrupt trigger ? writing 1 to bit r0 of the delayed interrupt request generation/clear register (dirr : r0 = 1) generates an interrupt request. ? writing 0 to bit r0 of the delayed interrupt request generation/clear register (dirr : r0 = 1) clears the interrupt request. interrupt control ? no enable/disable register is provided for this interrupt. interrupt flag ? set in bit r0 of the delayed interrupt request generation/clear register (dirr : r0) . ei 2 os support ? not supported by the extended intelligent i/o service (ei 2 os) . ??????? r0 internal data bus delayed interrupt request generation/ clear register (dirr) s r interrupt request signal interrupt request latch ? : undefined mb90560/565 series 50 9. 8/10-bit a/d converter ? overview of the 8/10-bit a/d converter ? the 8/10-bit a/d converter uses rc successive approximation to convert analog input voltages to an 8-bit or 10-bit digital value. ? the input signals can be selected from the eight analog input pin channels. ? 8/10-bit a/d converter functions ? 8/10-bit a/d converter conversion modes ? 8/10-bit a/d converter interrupts and ei 2 os : available a/d conversion time the minimum conversion time is 6.13 m s (for a 16 mhz machine clock, including sampling time) . the minimum sampling time is 2.0 m s (for a 16 mhz machine clock) conversion method rc successive approximation with sample & hold circuit resolution 8-bit or 10-bit, selectable analog input pins eight analog input pin channels are available. the input pin can be selected by the program. interrupts an interrupt request can be generated and ei 2 os invoked when a/d conversion completes. the conversion data protection function operates when a/d conversion is performed with the interrupt enabled. a/d conversion start trigger the conversion start trigger can be set from the following options : software, output of 16- bit reload timer 1 (rising edge) , or zero detection edge from 16-bit freerun timer. ei 2 os support supported by the extended intelligent i/o service (ei 2 os) . conversion mode single conversion mode operation scan conversion mode operation single-shot conversion mode 1 single-shot conversion mode 2 performs one conversion for the spec- ified channel (1 channel) then halts. sequentially performs one conversion for multiple channels (up to 8 channels can be set) , then halts. continuous conversion mode performs repeated conversions for the specified channel (1 channel) . performs repeated conversions for the specified channels (up to 8 channels can be set) . incremental conversion mode performs one conversion for the spec- ified channel (1 channel) then halts and waits for the next activation. sequentially performs one conversion for multiple channels (up to 8 channels can be set) , then halts and waits for the next activation. interrupt no. interrupt control register vector table address ei 2 os register name address lower upper bank #11 (0b h ) icr00 0000b0 h ffffd0 h ffffd1 h ffffd2 h mb90560/565 series 51 ? block diagram busy int inte paus sts1 sts0 strt rese- rved md1 md0 ans2 ans1 ans0 ane2 ane1 ane0 s10 st1 st0 ct1 ct0 d9 d7 d6 d4 d3 d2 d1 d0 p57/an7 p56/an6 p55/an5 p54/an4 p53/an3 p52/an2 p51/an1 p50/an0 avr av cc av ss d8 d5 f ? 2 2 6 2 a/d control status register (adcs0, adcs1) a/d data register (adcr0, adcs1) interrupt request signal #11 (0b h ) * 16-bit reload timer 1 output 16-bit freerun timer zero-detect clock selector decoder internal data bus analog channel selector sample & hold circuit comparator control circuit d/a converter f : machine clock * : interrupt number mb90560/565 series 52 10. rom mirror function selection module ? the rom mirror function selection module enables rom data in ff bank to be read by accessing 00 bank. ? rom mirror function selection module functions ? relationship between addresses in the rom mirror function ? block diagram function mirror setting address ? data in ffffff h to ff4000 h in ff bank can be read from 00ffff h to 004000 h in 00 bank. interrupts ? none ei 2 os support ? not supported by the extended intelligent i/o service (ei 2 os) . fe0000 h fe8000 h ff8000 h ff0000 h ff4000 h feffff h ffffff h ff bank mirrored rom data area rom area in mb90568 and mb90f568 rom area in mb90567 rom area in mb90562/a and mb90f562/b rom area in MB90561/a ??????? mi rom rom mirror function selection register (romm) internal data bus ff bank address data 00 bank address space mb90560/565 series 53 11. low power consumption (standby) modes ? the power consumption of f 2 mc-16lx devices can be reduced by various settings that control the operating clock selection. ? functions of each cpu operation mode cpu operation clock operation mode function pll clock normal run the cpu and peripheral functions operate using the oscillation clock (hclk) multiplied by the pll circuit. sleep the peripheral functions only operate using the oscillation clock (hclk) mul- tiplied by the pll circuit. pseudo-clock the timebase timer only operates using the oscillation clock (hclk) multi- plied by the pll circuit. stop the oscillation clock is stopped and the cpu and peripherals halt operation. main clock normal run the cpu and peripheral functions operate using the oscillation clock (hclk) divided into 2. sleep the peripheral functions only operate using the oscillation clock (hclk) di- vided into 2. stop the oscillation clock is stopped and the cpu and peripherals halt operation. cpu intermittent operation normal run the oscillation clock (hclk) divided into 2 operates intermittently for fixed time intervals. mb90560/565 series 54 12. 512 kbit flash memory ? this section describes the flash memory on the mb90f562/b and does not apply to evaluation and mask rom versions. ? the flash memory is located in bank ff in the cpu memory map. ? flash memory functions * : embedded algorithm is a trademark of advanced micro devices. ? sector configuration of flash memory function memory size ? 512 kbit (64 kbytes) memory configuration ? 64 kwords 8 bits or 32 kwords 16 bits sector configuration ? 16 kbytes + 8 kbytes + 8 kbytes + 32 kbytes sector protect function ? selectable for each sector programming algorithm ? automatic programming algorithm (embedded algorithm * : equivalent to mbm29f400ta) operation commands ? compatible with jedec standard commands ? includes an erase pause and restart function ? write/erase completion detection by data polling or toggle bit ? erasing by sector available (sectors can be combined in any combination) no. of write/erase cycles ? min. 10,000 guaranteed memory write/erase method ? can be written and erased using a parallel writer (ando denki af9704, af9705, af9706, af9708, and af9709) ? can be written and erased using a dedicated serial writer (yokogawa digital computer corporation af200, af210, af120, and af110) ? can be written and erased by the program interrupts ? write and erase completion interrupts ei 2 os support ? not supported by the extended intelligent i/o service (ei 2 os) . sa1 (32 kbyte) sa2 (8 kbyte) sa3 (8 kbyte) sa4 (16 kbyte) ff0000 h ff7fff h ff8000 h ff9fff h ffa000 h ffbfff h ffc000 h feffff h 70000 h 77fff h 78000 h 79fff h 7a000 h 7bfff h 7c000 h 7ffff h flash memory cpu address writer address * * : the writer address is the address to be used instead of the cpu address when writing data from a parallel flash memory writer. use the writer address when programming or erasing with a general-purpose parallel writer. mb90560/565 series 55 13. 1 mbit flash memory ? this section describes the flash memory on the mb90f568 and does not apply to evaluation and mask rom versions. ? the flash memory is located in banks fe to ff in the cpu memory map. ? flash memory functions * : embedded algorithm is a trademark of advanced micro devices. ? sector configuration of flash memory function memory size ? 1 mbit (128 kbytes) memory configuration ? 128 kwords 8 bits or 64 kwords 16 bits sector configuration ? 16 kbytes + 8 kbytes + 8 kbytes + 32 kbytes + 64 kbytes sector protect function ? selectable for each sector programming algorithm ? automatic programming algorithm (embedded algorithm* : equivalent to mbm29f400ta) operation commands ? compatible with jedec standard commands ? includes an erase pause and restart function ? write/erase completion detection by data polling or toggle bit ? erasing by sector available (sectors can be combined in any combination) no. of write/erase cycles ? min. 10,000 guaranteed memory write/erase method ? can be written and erased using a parallel writer (ando denki af9704, af9705, af9706, af9708, and af9709) ? can be written and erased using a dedicated serial writer (yokogawa digital computer corporation af200, af210, af120, and af110) ? can be written and erased by the program interrupts ? write and erase completion interrupts ei 2 os support ? not supported by the extended intelligent i/o service (ei 2 os) . sa0 (64 kbyte) sa1 (32 kbyte) sa2 (8 kbyte) sa3 (8 kbyte) sa4 (16 kbyte) fe0000 h fefff h ff0000 h ff7fff h ff8000 h ff9fff h ffa000 h ffbfff h ffc000 h feffff h 60000 h 6ffff h 70000 h 77fff h 78000 h 79fff h 7a000 h 7bfff h 7c000 h 7ffff h flash memory cpu address writer address * * : the writer address is the address to be used instead of the cpu address when writing data from a parallel flash memory writer. use the writer address when programming or erasing with a general-purpose parallel writer. mb90560/565 series 56 ? standard configuration for fujitsu standard serial on-board programming fujitsu standard serial on-board programming uses a flash microcontroller writer from yokogawa digital com- puter corporation (af220, af210, af120, or af210) . note : contact yokogawa digital computer corporation for details of the functions and operation of the flash microcontroller writer (af220, af210, af120, or af110) , standard connection cable (az221) , and connec- tors. ? pins used for fujitsu standard serial on-board programming symbol pin name function md2, md1, md0 mode input pins setting md2 = 1, md1 = 1, and md0 = 0 selects serial programming mode. x0, x1 oscillation input pin as flash memory serial programming mode uses the pll clock with the multiplier set to 1 as the internal cpu operation clock, the internal op- eration clock frequency is the same as the oscillation clock frequency. accordingly, the frequency that can be input to the high speed oscilla- tion input pin when performing serial programming is between 1 mhz and 16 mhz. p00, p01 write program activation pins input p00 = l level and p01 = h level. rst reset input pin ? sin1 serial data input pin uses uart0 and uart1 in clock synchronous mode. in programming mode, the pins used by uart0 in clock synchronous mode are sin1, sot1, and sck0. sot1 serial data output pin sck0 serial clock input pin c capacitor/power supply in- put pin capacitor pin for power supply stabilization. connect an external ce- ramic capacitor of approx. 0.1 m f. v cc power supply input pins if the user system provides the programming voltage (mb90f562 : 5 v 10 % , mb90f568 : 3 v 10 % ) , these do not need to be connected to the flash microcontroller writer. v ss gnd pin connect to common gnd with the flash microcontroller writer. host interface cable (az201) general-purpose cable (az221) flash microcontroller writer + memory card clock synchronous serial mb90f562/f562b/f568 user system can operate standalone rs232c mb90560/565 series 57 the control circuit shown in the figure is required when the p00, p01, sin1, sot1, and sck0 pins are used on the user system. use the /tics signal from the flash microcontroller writer to disconnect the user circuit during serial on-board programming. control circuit use the formula below to calculate the serial clock frequency able to be input to the mb90f562/f562b/f568. set up the flash microcontroller writer to use a serial clock input frequency that is permitted for the oscillation clock frequency you are using. permitted input serial clock frequency = 0.125 oscillation clock frequency ? maximum serial clock frequency ? system configuration of flash microcontroller writer (af220/af210/af120/af110) (supplier : yokoga- wa digital computer corporation) contact : yokogawa digital computer corporation tel : 042-333-6224 note : the af200 flash microcontroller writer is an obsolete model but can still be used with the ff201 control module. oscillation clock frequency maximum serial clock frequency that can be input to microcontroller maximum serial clock frequency that can be set on the af220/af210/af120/af110 maximum serial clock frequency that can be set on the af200 4 mhz 500 khz 500 khz 500 khz 8 mhz 1 mhz 850 khz 500 khz 16 mhz 2 mhz 1.25 mhz 500 khz model function unit af200/ac4p internal ethernet interface model /100 v to 220 v power adapter af210/ac4p standard model /100 v to 220 v power adapter af120/ac4p single key, internal ethernet interface model /100 v to 220 v power adapter af110/ac4p single key model /100 v to 220 v power adapter az221 special rs232c cable for connecting writer to pc/at az210 standard target probe (a) length : 1 m ff201 control module for fujitsu f 2 mc-16lx flash microcontrollers az290 remote controller az264 power supply regulator (mb90f568 : required to supply 3 v versions from the flash microcontroller writer.) /p2 2 mb pc card (option) supports flash memory sizes up to 128 kb /p4 4 mb pc card (option) supports flash memory sizes up to 512 kb 10 k w af220/af210/af120/af110 write control pin af220/af210/af120/af110 /tics pin mb90f562/f562b/f568 write control pin user mb90560/565 series 58 n electrical characteristics (mb90560 series) 1. absolute maximum ratings (v ss = av ss = 0.0 v) *1 : av cc and avr must not exceed v cc . also, avr must not exceed av cc . *2 : v i and v o must not exceed v cc + 0.3 v. *3 : the maximum output current is the peak value for a single pin. *4 : pins other than p30/rto0 to p35/rto5 *5 : p30/rto0 to p35/rto5 pins warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. parameter symbol rating unit remarks min. max. power supply voltage v cc v ss - 0.3 v ss + 6.0 v av cc v ss - 0.3 v ss + 6.0 v v cc 3 av cc *1 avr v ss - 0.3 v ss + 6.0 v av cc 3 avr 3 0 v *1 input voltage v i v ss - 0.3 v ss + 6.0 v *2 output voltage v o v ss - 0.3 v ss + 6.0 v *2 l level maximum output current i ol1 ? 15 ma *3, *4 i ol2 ? 20 ma *3, *5 l level average output current i olav1 ? 4ma average value (operating current operating ratio) *4 i olav2 ? 12 ma average value (operating current operating ratio) *5 l level total maximum output current s i ol ? 100 ma l level total average output current s i olav ? 50 ma average value (operating current operating ratio) h level maximum output current i oh ?- 15 ma *3 h level average output current i ohav ?- 4ma average value (operating current operating ratio) h level total maximum output current s i oh ?- 100 ma h level total average output current s i ohav ?- 50 ma average value (operating current operating ratio) power consumption pd ? 300 mw operating temperature t a - 40 + 85 c storage temperature tstg - 55 + 150 c mb90560/565 series 59 2. recommended operating conditions (v ss = av ss = 0.0 v) warning: the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the devices electrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating condition ranges. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand. parameter symbol value unit remarks min. max. power supply voltage v cc 3.0 5.5 v normal operation (mb90562, 562a, 561, 561a, and v560) 4.5 5.5 v normal operation (mb90f562 and f562b) v cc 3.0 5.5 v maintaining state in stop mode input h voltage v ih 0.7 v cc v cc + 0.3 v cmos input pin v ihs 0.8 v cc v cc + 0.3 v cmos hysteresis input pin v ihm v cc - 0.3 v cc + 0.3 v md input pin input l voltage v il v ss - 0.3 0.3 v cc v cmos input pin v ils v ss - 0.3 0.2 v cc v cmos hysteresis input pin v ilm v ss - 0.3 v ss + 0.3 v md input pin smoothing capacitor c s 0.1 1.0 m f use a ceramic capacitor or other capacitor with equivalent frequency characteristics. the capacitance of the smoothing capacitor connected to the v cc pin must be greater than c s . operating temperature t a - 40 + 85 c c c s ? c pin diagram mb90560/565 series 60 3. dc characteristics (t a = - 40 c to + 85 c, v cc = 5.0 v 10 % , v ss = av ss = 0.0 v) * : value when low power mode bits (lpm0, 1) is set to 01 with an internal operating frequency of 4 mhz. note : current values are provisional and are subject to change without notice to allow for improvements to the characteristics. the power supply current is measured with an external clock. parameter sym- bol pin name condition value unit remarks min. typ. max. output h voltage v oh all output pins v cc = 4.5 v i oh = - 2.0 ma v cc - 0.5 ?? v output l voltage v ol1 pins other than p30/ rto0 to p35/rto5 v cc = 4.5 v i ol1 = 2.0 ma ?? 0.4 v v ol2 p30/rto0 to p35/ rto5 v cc = 4.5 v i ol2 = 12.0 ma ?? 0.8 v input leak current i il all output pins v cc = 5.5 v v ss < v i < v cc - 5 ? 5 m a power supply current * i cc v cc for v cc = 5 v, internal frequency = 16 mhz, normal operation ? 50 80 ma mb90562/a, MB90561/a ? 40 50 ma mb90f562/b for v cc = 5 v, internal frequency = 16 mhz, a/d operation in progress ? 55 85 ma mb90562/a, MB90561/a ? 45 55 ma mb90f562/b flash write or erase ? 45 60 ma mb90f562/b i ccs for v cc = 5 v, internal frequency = 16 mhz, sleep mode ? 15 20 ma mb90562/a, MB90561/a mb90f562/b * i cch stop mode, ta = 25 c ? 520 m a input capacitance c in other than av cc , av ss , c, v cc , and v ss ?? 10 80 pf pull-up resistor r up p00 to p07 p10 to p17 rst , md0, md1 ? 15 30 100 k w pull-down resistor r down md2 ? 15 30 100 k w mb90560/565 series 61 4. ac characteristics (1) clock timings (t a = - 40 c to + 85 c, v cc = 5.0 v 10 % , v ss = av ss = 0.0 v) parameter sym bol pin name condi- tion value unit remarks min. typ. max. clock frequency f c x0, x1 ? 3 ? 16 mhz with a pll circuit 1 ? 16 without a pll circuit clock cycle time t hcyl x0, x1 62.5 ? 333 ns with a pll circuit 62.5 ? 1000 without a pll circuit input clock pulse width p wh p wl x0 10 ?? ns recommended duty ratio = 30 % to 70 % input clock rise/fall time tcr tcf x0 ?? 5ns when using an external clock internal operating clock frequency f cp ? 1.5 ? 16 mhz when using a main clock internal operating clock cycle time t cp ? 62.5 ? 333 ns when using a main clock 0.8 v cc 0.2 v cc t cf t cr t hcyl p wh p wl x0 ? x0 and x1 clock timing mb90560/565 series 62 the ac ratings are specified for the following measurement reference voltages. ? pll guaranteed operation range relationship between internal operating clock frequency and power supply voltage relationship between oscillation frequency and internal operating clock frequency 5.5 4.5 3.3 3.0 13 8 12 16 guaranteed operation range for mb90f562/b pll guaranteed operation range pll guaranteed operation range a/d converter guaranteed operation range guaranteed operation range for MB90561/a and mb90562/a guaranteed operation range for mb90v560 supply voltage v cc (v) internal clock f cp (mhz) 16 12 8 4 3 2 1234 6 8 12 16 4 3 2 1 no multiplier internal clock f cp (mhz) source oscillation clock f c (mhz) 0.5 0.8 v cc 0.2 v cc 2.4 v 0.8 v 0.7 v cc 0.3 v cc ? input signal waveform hysteresis input pin pins other than hysteresis input or md input pins ? output signal waveform output pin mb90560/565 series 63 (2)reset (t a = - 40 c to + 85 c, v cc = 5.0 v 10 % , v ss = av ss = 0.0 v) *: oscillator oscillation time is the time to reach 90 % amplitude. for a crystal oscillator, this is a few to several dozen ms; for a far/ceramic oscillator, this is several hundred m s to a few ms, and for an external clock this is 0 ms. parameter symbol pin name condition value unit remarks min. max. reset input time t rsth rst ? 16 t cp ? ns in normal operation oscillator oscillation time* + 16 t cp ? ms in stop mode rst 0.2 v cc t rstl 0.2 v cc ? in normal operation rst x0 16 tcp t rstl 0.2vcc 0.2vcc internal operation clock internal reset 90 % of amplitude oscillator oscillation time oscillator stabilization wait time execution of the instruction ? in stop mode mb90560/565 series 64 (3) power-on reset (t a = - 40 c to + 85 c, v cc = 5.0 v 10 % , v ss = av ss = 0.0 v) * : v cc must be less than 0.2 v before power-on. notes : the above rating values are for generating a power-on reset. some internal registers are only initialized by a power-on reset. always apply the power supply in accordance with the above ratings if you wish to initialize these registers. parameter symbol pin name condi- tion value unit remarks min. max. power supply rise time t r v cc ? 0.05 30 ms power supply cutoff time t off v cc 4 ? ms for repeated operation v cc v cc 3.0 v v ss t r 0.2 v 0.2 v 2.7 v t off 0.2 v maintain ram data recommended rate of voltage rise is 50 mv/ms or less. sudden changes in the power supply voltage may cause a power-on reset. the recommended practice if you wish to change the power supply voltage while the device is operating is to raise the voltage smoothly as shown below. also, changes to the supply voltage should be performed when the pll clock is not in use. the pll clock may be used, however, if the rate of voltage change is 1 v/s or less. mb90560/565 series 65 (4) uart0, uart1, and i/o expansion serial timings (t a = - 40 c to + 85 c, v cc = 5.0 v 10 % , v ss = av ss = 0.0 v) notes : these are the ac ratings for clk synchronous mode. c l is the load capacitor connected to the pin for testing. t cp is the machine cycle period (unit = ns) parameter symbol pin name condition value unit remarks min. max. serial clock cycle time t scyc sck0, sck1 internal shift clock mode, output pin load is cl = 80 pf + 1 ttl 8 t cp ? ns sck ? sot delay time t slov sck0, sck1 sot0, sot1 - 80 80 ns valid sin ? sck - t ivsh sck0, sck1 sin0, sin1 100 ? ns sck - ? valid sin hold time t shix sck0, sck1 sin0, sin1 60 ? ns serial clock h pulse width t shsl sck0, sck1 external shift clock mode, output pin load is cl = 80 pf + 1 ttl 4 t cp ? ns serial clock l pulse width t slsh sck0, sck1 4 t cp ? ns sck ? sot delay time t slov sck0, sck1 sot0, sot1 ? 150 ns valid sin ? sck - t ivsh sck0, sck1 sin0, sin1 60 ? ns sck - ? valid sin hold time t shix sck0, sck1 sin0, sin1 60 ? ns mb90560/565 series 66 ? internal shift clock mode ? external shift clock mode sck sot sin t scyc t slov t ivsh t shix 0.8 v 0.8 v 2.4 v 2.4 v 0.8 v 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc sck sot sin t slsh t shsl t slov t ivsh t shix 0.2 v cc 0.2 v cc 0.8 v cc 0.8 v cc 2.4 v 0.8 v 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc mb90560/565 series 67 (5) timer input timings (t a = - 40 c to + 85 c, v cc = 5.0 v 10 % , v ss = av ss = 0.0 v) (6) timer output timings (t a = - 40 c to + 85 c, v cc = 5.0 v 10 % , v ss = av ss = 0.0 v) (7) trigger input timings (t a = - 40 c to + 85 c, v cc = 5.0 v 10 % , v ss = av ss = 0.0 v) parameter symbol pin name condi- tion value unit remarks min. max. input pulse width t tiwh , t tiwl frck, in0, in1, tin0, tin1 ? 4 t cp ? ns parameter symbol pin name condi- tion value unit remarks min. max. clk - ? t out change time t to rto0 to rto5, ppg0 to ppg5, to0 to to1 ? 30 ? ns parameter symbol pin name condition value unit remarks min. max. input pulse width t trgl int0 to int7, in0 to in3 ? 5 t cp ? ns in normal operation 1 ?m s in stop mode 0.8 v cc 0.8 v cc 0.2 v cc 0.2 v cc t tiwh t tiwl clk t out 2.4 v t to 2.4 v 0.8 v 0.8 v cc 0.8 v cc 0.2 v cc 0.2 v cc t trgh t trgl mb90560/565 series 68 5. electrical characteristics for the a/d converter (t a = - 40 c to + 85 c, 3.0 v avr, v cc = av cc = 5.0 v 10 % , v ss = av ss = 0.0 v) * : current when a/d converter is not used and cpu is in stop mode (v cc = av cc = avr = 5.0 v) notes : the l reference voltage is fixed to av ss . the relative error increases as avr becomes smaller. ensure that the output impedance of the external circuit connected to the analog input meets the following condition : output impedance of external circuit 10 k w (sampling time = 4.0 m s) if the output impedance of the external circuit is too high, the analog voltage sampling time may be too short. parameter symbol pin name value unit remarks min. typ. max. resolution ?? ? 10 ? bit total error ?? ?? 5.0 lsb non-linearity error ?? ?? 2.5 lsb differential linearity error ?? ?? 1.9 lsb zero transition voltage v ot an0 to an7 av ss - 3.5 lsb + 0.5 av ss + 4.5 lsb mv 1 lsb = avrh/1024 full-scale transition voltage v fst an0 to an7 avr - 6.5 lsb avr - 1.5 lsb avr + 1.5 lsb mv conversion time ?? ? 176 t cp ? ns sampling time ?? ? 64 t cp ? ns analog port input current i ain an0 to an7 ?? 10 m a analog input voltage v ain an0 to an7 0 ? avr v reference voltage ? avr 2.7 ? av cc v power supply current i a av cc ? 5 ? ma i ah av cc ?? 5 m a* reference voltage supply current i r avr ? 400 ?m a i rh avr ?? 5 m a* variation between channels ? an0 to an7 ?? 4lsb ? equivalent circuit of analog input circuit c r on analog input comparator MB90561/a, mb90562/a r on = 2.2 k w approx. c = 45 pf approx. mb90f562 r on = 3.2 k w approx. c = 30 pf approx. mb90f562/b r on = 2.6 k w approx. c = 28 pf approx. note : the values listed are an indication only. mb90560/565 series 69 6. flash memory erase and programming performance parameter condition value units remarks min typ max sector erase time t a = + 25 c vcc = 5.0 v ? 115s excludes 00h programming prior erasure chip erase time ? 5 ? s excludes 00h programming prior erasure word (16 bit width) programming time ? 16 3,600 m s excludes system-level overhead erase/program cycle ? 10,000 ?? cycle data holding time ? 100,000 ?? h mb90560/565 series 70 n electrical characteristics (mb90565 series) 1. absolute maximum ratings (v ss = av ss = 0.0 v) *1 : av cc and avr must not exceed v cc . also, avr must not exceed av cc . *2 : v i and v o must not exceed v cc + 0.3 v. *3 : the maximum output current is the peak value for a single pin. warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. parameter symbol rating unit remarks min. max. power supply voltage v cc v ss - 0.3 v ss + 4.0 v av cc v ss - 0.3 v ss + 4.0 v v cc 3 av cc *1 avr v ss - 0.3 v ss + 4.0 v av cc 3 avr 3 0 v *1 input voltage v i v ss - 0.3 v ss + 4.0 v *2 output voltage v o v ss - 0.3 v ss + 4.0 v *2 l level maximum output current i ol ? 15 ma *3 l level average output current i olav ? 4ma average value (operating current operating ratio) l level total maximum output current s i ol ? 100 ma l level total average output current s i olav ? 50 ma average value (operating current operating ratio) h level maximum output current i oh ?- 15 ma *3 h level average output current i ohav ?- 4ma average value (operating current operating ratio) h level total maximum output current s i oh ?- 100 ma h level total average output current s i ohav ?- 50 ma average value (operating current operating ratio) power consumption pd ? 300 mw operating temperature t a - 40 + 85 c storage temperature tstg - 55 + 150 c mb90560/565 series 71 2. recommended operating conditions (v ss = av ss = 0.0 v) warning: the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the devices electrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating condition ranges. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand. parameter symbol value unit remarks min. max. power supply voltage v cc 3.0 3.6 v normal operation (mb90v560) 2.7 3.6 v normal operation (mb90f568, mb90567 and mb90568) 2.5 3.6 v maintaining state in stop mode input h voltage v ih 0.7 v cc v cc + 0.3 v cmos input pin v ihs 0.8 v cc v cc + 0.3 v cmos hysteresis input pin v ihm v cc - 0.3 v cc + 0.3 v md input pin input l voltage v il v ss - 0.3 0.3 v cc v cmos input pin v ils v ss - 0.3 0.2 v cc v cmos hysteresis input pin v ilm v ss - 0.3 v ss + 0.3 v md input pin operating temperature t a - 40 + 85 c mb90560/565 series 72 3. dc characteristics (t a = - 40 c to + 85 c, v cc = 2.7 v to 3.6 v, v ss = av ss = 0.0 v) * : value when low power mode bits (lpm0, 1) are set to 01 with an internal operating frequency of 8 mhz. (continued) parameter sym bol pin name condition value unit remarks min. typ. max. output h voltage v oh all output pins v cc = 3.0 v i oh = - 2.0 ma v cc - 0.5 v cc - 0.3 ? v output l voltage v ol all output pins v cc = 3.0 v i ol = 2.0 ma ? 0.2 0.4 v input leak current i il all output pins v cc = 3.0 v v ss < v i < v cc - 5 - 15 m a power supply current* i cc v cc for v cc = 3.3 v, internal frequency = 8 mhz, normal operation ? 14 22 ma mb90567/568 for v cc = 3.3 v, internal frequency = 16 mhz, normal operation ? 27 40 ma mb90567/568 for v cc = 3.3 v, internal frequency = 8 mhz, a/d operation in progress ? 18 27 ma mb90567/568 for v cc = 3.3 v, internal frequency = 16 mhz, a/d operation in progress ? 32 45 ma mb90567/568 for v cc = 3.3 v, internal frequency = 8 mhz, normal operation ? 18 28 ma mb90f568 for v cc = 3.3 v, internal frequency = 16 mhz, normal operation ? 36 45 ma mb90f568 for v cc = 3.3 v, internal frequency = 8 mhz, a/d operation in progress ? 23 33 ma mb90f568 for v cc = 3.3 v, internal frequency = 16 mhz, a/d operation in progress ? 41 50 ma mb90f568 flash write or erase ? 40 50 ma mb90f568 i ccs for v cc = 3.3 v, internal frequency = 8 mhz, sleep mode ? 610ma mb90567/568 mb90f568 * for v cc = 3.3 v, internal frequency = 16 mhz, sleep mode ? 14 20 ma mb90567/568 mb90f568 * i cch stop mode, t a = 25 c ? 520 m a mb90560/565 series 73 (continued) note : current values are provisional and are subject to change without notice to allow for improvements to the characteristics. the power supply current is measured with an external clock. parameter sym- bol pin name condition value unit remarks min. typ. max. pull-up resistor r up p00 to p07 p10 to p17 rst , md0, md1 ? 20 65 200 k w pull-down resistor r down md2 ? 20 65 200 k w mb90560/565 series 74 4. ac characteristics (1) clock timings (mb90567/568/f568 : t a = - 40 c to + 85 c, v cc = 2.7 v to 3.6 v, v ss = av ss = 0.0 v) (mb90v560 : t a = + 25 c, v cc = 2.7 v to 3.6 v, v ss = av ss = 0.0 v) parameter sym bol pin name condi- tion value unit remarks min. typ. max. clock frequency f c x0, x1 ? 3 ? 12 mhz mb90v560 3 ? 16 mhz mb90567/568 mb90f568 clock cycle time t hcyl x0, x1 83.3 ? 333 ns mb90v560 62.5 ? 333 ns mb90567/568 mb90f568 input clock pulse width p wh p wl x0 10 ?? ns recommended duty ratio = 30 % to 70 % input clock rise/fall time tcr tcf x0 ?? 5ns when using an external clock internal operating clock frequency f cp ? 1.5 ? 12 mhz mb90v560 1.5 ? 16 mhz mb90567/568 mb90f568 internal operating clock cycle time t cp ? 83.3 ? 666 ns mb90v560 62.5 ? 666 ns mb90567/568 mb90f568 0.8 v cc 0.2 v cc t cf t cr t hcyl p wh p wl x0 ? x0 and x1 clock timing mb90560/565 series 75 the ac ratings are specified for the following measurement reference voltages. ? pll guaranteed operation range relationship between internal operating clock frequency and power supply voltage relationship between oscillation frequency and internal operating clock frequency 3.6 3.0 2.7 1.5 3 8 12 16 pll guaranteed operation range (mb90567/568/f568 : 3.0 v to 3.6 v, f cp = 3 mhz to 16 mhz) (mb90v560 : 3.0 v to 3.6 v, f cp = 3 mhz to 12 mhz) pll guaranteed operation range a/d converter guaranteed operation rang e guaranteed operation range for mb90567/568/f568 (3.0 v to 3.6 v, f cp = 1.5 mhz to 16 mhz) (2.7 v to 3.6 v, f cp = 1.5 mhz to 8 mhz) supply voltage v cc (v) internal clock f cp (mhz) guaranteed operation range for mb90v560 (3.0 v to 3.6 v, f cp = 1.5 mhz to 12 mhz) 16 12 8 6 9 4 3 1.5 2 34 6 8 12 16 4 3 2 1 no multiplier internal clock f cp (mhz) source oscillation clock f c (mhz) 0.8 v cc 0.2 v cc 2.4 v 0.8 v 0.7 v cc 0.3 v cc ? input signal waveform hysteresis input pin pins other than hysteresis input or md input pins ? output signal waveform output pin mb90560/565 series 76 (2) reset (t a = - 40 c to + 85 c, v cc = 2.7 v to 3.6 v, v ss = av ss = 0.0 v) *: oscillator oscillation time is the time to reach 90 % amplitude. for a crystal oscillator, this is a few to several dozen ms; for a far/ceramic oscillator, this is several hundred m s to a few ms, and for an external clock this is 0 ms. parameter symbol pin name condition value unit remarks min. max. reset input time t rstl rst ? 16 t cp ? ns in normal operation oscillator oscillation time* + 16 t cp ? ms in stop mode rst 0.2 v cc t rstl 0.2 v cc ? in normal operation rst x0 16 tcp t rstl 0.2vcc 0.2vcc internal operation clock internal reset 90 % of amplitude oscillator oscillation time oscillator stabilization wait time execution of the instruction ? in stop mode mb90560/565 series 77 (3) power-on reset (t a = - 40 c to + 85 c, v cc = 2.7 v to 3.6 v, v ss = av ss = 0.0 v) * : v cc must be less than 0.2 v before power-on. notes : the above rating values are for generating a power-on reset. some internal registers are only initialized by a power-on reset. always apply the power supply in accordance with the above ratings if you wish to initialize these registers. parameter symbol pin name condi- tion value unit remarks min. max. power supply rise time t r v cc * ? 0.05 30 ms power supply cutoff time t off v cc 4 ? ms for repeated operation v cc v cc 2.5 v v ss t r 0.2 v 0.2 v 2.7 v t off 0.2 v maintain ram data recommended rate of voltage rise is 50 mv/ms or less. sudden changes in the power supply voltage may cause a power-on reset. the recommended practice if you wish to change the power supply voltage while the device is operating is to raise the voltage smoothly as shown below. also, changes to the supply voltage should be performed when the pll clock is not in use. the pll clock may be used, however, if the rate of voltage change is 1 v/s or less. mb90560/565 series 78 (4) uart0 and uart1 (t a = - 40 c to + 85 c, v cc = 2.7 v to 3.6 v, v ss = av ss = 0.0 v) notes : these are the ac ratings for clk synchronous mode. cv is the load capacitor connected to the pin for testing. t cp is the machine cycle period (unit = ns) parameter symbol pin name condition value unit remarks min. max. serial clock cycle time t scyc sck0, sck1 internal shift clock mode, output pin load is c l = 80 pf + 1 ttl 8 t cp ? ns sck ? sot delay time t slov sck0, sck1 sot0, sot1 - 80 80 ns valid sin ? sck - t ivsh sck0, sck1 sin0, sin1 100 ? ns sck - ? valid sin hold time t shix sck0, sck1 sin0, sin1 60 ? ns serial clock h pulse width t shsl sck0, sck1 external shift clock mode, output pin load is c l = 80 pf + 1 ttl 4 t cp ? ns serial clock l pulse width t slsh sck0, sck1 4 t cp ? ns sck ? sot delay time t slov sck0, sck1 sot0, sot1 ? 150 ns valid sin ? sck - t ivsh sck0, sck1 sin0, sin1 60 ? ns sck - ? valid sin hold time t shix sck0, sck1 sin0, sin1 60 ? ns mb90560/565 series 79 ? internal shift clock mode ? external shift clock mode sck sot sin t scyc t slov t ivsh t shix 0.8 v 0.8 v 2.4 v 2.4 v 0.8 v 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc sck sot sin t slsh t shsl t slov t ivsh t shix 0.2 v cc 0.2 v cc 0.8 v cc 0.8 v cc 2.4 v 0.8 v 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc mb90560/565 series 80 (5) timer input timings (t a = - 40 c to + 85 c, v cc = 2.7 v to 3.6 v, v ss = av ss = 0.0 v) (6) timer output timings (t a = - 40 c to + 85 c, v cc = 2.7 v to 3.6 v, v ss = av ss = 0.0 v) (7) trigger input timings (t a = - 40 c to + 85 c, v cc = 2.7 v to 3.6 v, v ss = av ss = 0.0 v) parameter symbol pin name condi- tion value unit remarks min. max. input pulse width t tiwh , t tiwl frck, tin0, tin1 ? 4 t cp ? ns parameter symbol pin name condition value unit remarks min. max. clk - ? t out change time t to rto0 to rto5, ppg0 to ppg5 to0, to1 ? 30 ? ns parameter symbol pin name condition value unit remarks min. max. input pulse width t trgl int0 to int7, in0 to in3 ? 5 t cp ? ns in normal operation 1 ?m s in stop mode 0.8 v cc frck tin0 to 1 0.8 v cc 0.2 v cc 0.2 v cc t tiwh t tiwl clk t out 2.4 v t to 2.4 v 0.8 v 0.8 v cc int0 to int 7 in0 to in 3 0.8 v cc 0.2 v cc 0.2 v cc t trgh t trgl mb90560/565 series 81 5. electrical characteristics for the a/d converter (mb90567/568/f568 : t a = - 40 c to + 85 c, 2.7 v avr, v cc = av cc = 2.7 v to 3.6 v, v ss = av ss = 0.0 v) (mb90v560 : t a = + 25 c, 3.0 v avr, v cc = av cc = 3.0 v to 3.6 v, v ss = av ss = 0.0 v) * : current when a/d converter is not used and cpu is in stop mode (v cc = av cc = avr = 3.3 v) notes : the l reference voltage is fixed to av ss . the relative error increases as avr becomes smaller. ensure that the output impedance of the external circuit connected to the analog input meets the following condition : output impedance of mb90f568 external circuit 14 k w (sampling time = 4 m s) output impedance of mb90567/568 external circuit 7 k w (sampling time = 4 m s) if the output impedance of the external circuit is too high, the analog voltage sampling time may be too short. parameter symbol pin name value unit remarks min. typ. max. resolution ?? ?? 10 bit total error ?? ?? 3.0 lsb non-linearity error ?? ?? 2.5 lsb differential linearity error ?? ?? 1.9 lsb zero transition voltage v ot an0 to an7 av ss - 1.5 lsb av ss + 0.5 av ss + 2.5 lsb mv 1 lsb = avrh/1024 full-scale transition voltage v fst an0 to an7 avr - 3.5 lsb avr - 1.5 lsb avr + 0.5 lsb mv conversion time ?? ? 66 t cp ? ns sampling time ?? ? 32 t cp ? ns analog port input current i ain an0 to an7 ?? 10 m a analog input voltage v ain an0 to an7 0 ? avr v reference voltage ? avr 2.7 ? av cc v power supply current i a av cc ? 15ma i ah av cc ?? 5 m a* reference voltage supply current i r avr ? 100 200 m a i rh avr ?? 5 m a* variation between channels ? an0 to an7 ?? 4lsb mb90560/565 series 82 ? equivalent circuit of analog input circuit c r on analog input comparator mb90567/568/f568 r on = 7.1 k w approx. c = 48.3 pf approx. note : the values listed are an indication only. mb90560/565 series 83 6. flash memory erase and programming performance ? points to note regarding the mb90f568, 567, and 568 specifications this section describes the specification differences between the mb90f568/567/568 and the mb90f562/f562b/ 562/562a/561/561a. (1) functional differences 1) the 5 v to 3 v regulator has been removed in the mb96565 series. the c pin has been changed to an n.c. pin. 2) the a/d converter unit in the mb96565 series has changed from a 5 v version to a 3 v version. however, the conversion time and sampling time remain the same. 3) the maximum voltage that can be applied to i/o pins has changed from 5 v to 3 v in the mb96565 series. 4) added transfer counter clear function to uart in the mb96565 series. this function restores the uart to its initial state when 0 is written to the uart reset bit. (2) points to note when using the devices the mb90f562, f562b, and f568 use p60 (14) as sin1, p61 (15) as sot1, and p40 (60) as sck0 when performing on-board programming. use the following pin settings when performing on-board programming. * : these settings are for using a yokogawa digital computer corporation writer for on-board programming. alter- natively, writing can be performed from a pc, but a special write program is required. parameter condition value units remarks min typ max sector erase time t a = + 25 c vcc = 3.3 v ? 115s excludes 00h programming prior erasure chip erase time ? 5 ? s excludes 00h programming prior erasure word (16 bit width) programming time ? 16 3,600 m s excludes system-level overhead erase/program cycle ? 10,000 ?? cycle data holding time ? 100,000 ?? h pin name pin i/o level* remarks md2 h level serial write mode settings md1 h level md0 l level sin1 serial data input normally shared with p60 sot1 serial data output normally shared with p61 sck0 serial clock normally shared with p40 p00 l level p01 h level input l level for pc writing mb90560/565 series 84 n example characteristics (continued) mb90f568 i cc - v cc mb90568 i cc - v cc mb90f568 i ccs - v cc 60 50 40 30 20 10 0 2 2.5 3 3.5 v cc (v) i cc (ma) 4 4.5 16 mhz 12 mhz 8 mhz 4 mhz 2 mhz t a = + 25 c 40 35 30 25 20 15 10 5 0 2 2.5 3 3.5 v cc (v) i cc3 (ma) 4 4.5 16 mhz 12 mhz 8 mhz 4 mhz 2 mhz t a = + 25 c 20 18 16 14 12 10 8 6 4 2 0 2 2.5 3 3.5 v cc (v) i ccs (ma) 4 4.5 16 mhz 12 mhz 8 mhz 4 mhz 2 mhz t a = + 25 c mb90560/565 series 85 (continued) mb90568 i ccs - v cc mb90f562 i cc - v cc mb90562 i cc - v cc 18 16 14 12 10 8 6 4 2 0 2 2.5 3 3.5 v cc (v) i ccs (ma) 4 4.5 16 mhz 12 mhz 8 mhz 4 mhz 2 mhz t a = + 25 c 2.5 3 3.5 4 4.5 v cc (v) 5 5.5 6 6.5 i cc (ma) f = 16 mhz f = 12 mhz f = 10 mhz f = 8 mhz f = 4 mhz f = 2 mhz 40 35 30 25 20 15 10 5 0 t a = + 25 c 2.5 3 3.5 4 4.5 v cc (v) 5 5.5 6 6.5 i cc (ma) 70 60 50 40 30 20 10 0 f = 16 mhz f = 12 mhz f = 10 mhz f = 8 mhz f = 4 mhz f = 2 mhz t a = + 25 c mb90560/565 series 86 (continued) mb90f562 i ccs - v cc mb90562 i ccs - v cc 2.5 3 3.5 4 4.5 v cc (v) 5 5.5 6 6.5 i ccs (ma) 16 14 12 10 8 6 4 2 0 f = 16 mhz f = 12 mhz f = 10 mhz f = 8 mhz f = 4 mhz f = 2 mhz t a = + 25 c 2.5 3 3.5 4 4.5 v cc (v) 5 5.5 6 6.5 i ccs (ma) 30 25 20 15 10 5 0 f = 16 mhz f = 12 mhz f = 10 mhz f = 8 mhz f = 4 mhz f = 2 mhz t a = + 25 c mb90560/565 series 87 n ordering information ? mb90560 series ? mb90565 series part no. package remarks MB90561p mb90562p MB90561ap mb90562ap mb90f562p mb90f562bp 64-pin plastic sh-dip (dip-64p-m01) MB90561pf mb90562pf MB90561apf mb90562apf mb90f562pf mb90f562bpf 64-pin plastic qfp (fpt-64p-m06) MB90561pfm mb90562pfm MB90561apfm mb90562apfm mb90f562pfm mb90f562bpfm 64-pin plastic lqfp (fpt-64p-m09) part no. package remarks mb90567pf mb90568pf mb90f568pf 64-pin plastic qfp (fpt-64p-m06) mb90567pfm mb90568pfm mb90f568pfm 64-pin plastic lqfp (fpt-64p-m09) mb90560/565 series 88 n package dimensions (continued) 64-pin plastic qfp (fpt-64p-m06) note : pins width and pins thickness include plating thickness. dimensions in mm (inches) c 2001 fujitsu limited f64013s-c-4-4 0.20(.008) m 18.70?.40 (.736?016) 14.00?.20 (.551?008) 1.00(.039) index 0.10(.004) 119 20 32 52 64 33 51 20.00?.20(.787?008) 24.70?.40(.972?016) 0.42?.08 (.017?003) 0.17?.06 (.007?002) 0~8 1.20?.20 (.047?008) 3.00 +0.35 ?.20 (mounting height) .118 +.014 ?008 0.25 +0.15 ?.20 .010 +.006 ?008 (stand off) details of "a" part "a" 0.10(.004) mb90560/565 series 89 (continued) 64-pin plastic lqfp (fpt-64p-m09) note : pins width and pins thickness include plating thickness. dimensions in mm (inches) c 2001 fujitsu limited f64018s-c-2-4 0.65(.026) 0.10(.004) 116 17 32 49 64 33 48 12.00?.10(.472?004)sq 14.00?.20(.551?008)sq index 0.32?.05 (.013?002) m 0.13(.005) 0.145?.055 (.0057?0022) "a" .059 ?004 +.008 ?.10 +0.20 1.50 0~8 0.25(.010) (mounting height) 0.50?.20 (.020?008) 0.60?.15 (.024?006) 0.10?.10 (.004?004) details of "a" part (stand off) 0.10(.004) mb90560/565 series 90 (continued) 64-pin plastic sh-dip (dip-64p-m01) note : pins width and pins thickness include plating thickness. dimensions in mm ( inches ) c 2001 fujitsu limited d64001s-c-4-5 58.00 +0.22 ?.55 +.009 ?022 2.283 17.00?.25 (.669?010) 3.30 +0.20 ?.30 .130 ?012 +.008 +.028 ?008 .195 ?.20 +0.70 4.95 +.016 ?008 .0543 ?.20 +0.40 1.378 1.778(.0700) 0.47?.10 (.019?004) 1.00 +0.50 ? .039 ?0 +.020 +.020 ?007 .028 ?.19 +0.50 0.70 19.05(.750) (.011?004) 0.27?.10 0~15 index-2 index-1 m 0.25(.010) mb90560/565 series fujitsu limited all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. the products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). please note that fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade law of japan, the prior authorization by japanese government will be required for export of those products from japan. f 0204 ? fujitsu limited printed in japan |
Price & Availability of MB90561
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |